psoc62xa/
hsiom.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright OxidOS Automotive 2025 SRL.
4
5use kernel::utilities::registers::{
6    interfaces::ReadWriteable, register_bitfields, register_structs, ReadWrite,
7};
8use kernel::utilities::StaticRef;
9
10register_structs! {
11    HsiomRegisters {
12        (0x000 => _reserved0),
13        (0x050 => prt5_port_sel0: ReadWrite<u32, PRT5_PORT_SEL0::Register>),
14        (0x054 => _reserved3),
15        (0x2000 => amux_split_ctl_0: ReadWrite<u32, AMUX_SPLIT_CTL0::Register>),
16        (0x2004 => amux_split_ctl_1: ReadWrite<u32, AMUX_SPLIT_CTL1::Register>),
17        (0x2008 => amux_split_ctl_2: ReadWrite<u32, AMUX_SPLIT_CTL2::Register>),
18        (0x200C => amux_split_ctl_3: ReadWrite<u32, AMUX_SPLIT_CTL3::Register>),
19        (0x2010 => amux_split_ctl_4: ReadWrite<u32, AMUX_SPLIT_CTL4::Register>),
20        (0x2014 => amux_split_ctl_5: ReadWrite<u32, AMUX_SPLIT_CTL5::Register>),
21        (0x2018 => amux_split_ctl_6: ReadWrite<u32, AMUX_SPLIT_CTL6::Register>),
22        (0x201C => amux_split_ctl_7: ReadWrite<u32, AMUX_SPLIT_CTL7::Register>),
23        (0x2020 => amux_split_ctl_8: ReadWrite<u32, AMUX_SPLIT_CTL8::Register>),
24        (0x2024 => amux_split_ctl_9: ReadWrite<u32, AMUX_SPLIT_CTL9::Register>),
25        (0x2028 => amux_split_ctl_10: ReadWrite<u32, AMUX_SPLIT_CTL10::Register>),
26        (0x202C => amux_split_ctl_11: ReadWrite<u32, AMUX_SPLIT_CTL11::Register>),
27        (0x2030 => amux_split_ctl_12: ReadWrite<u32, AMUX_SPLIT_CTL12::Register>),
28        (0x2034 => amux_split_ctl_13: ReadWrite<u32, AMUX_SPLIT_CTL13::Register>),
29        (0x2038 => amux_split_ctl_14: ReadWrite<u32, AMUX_SPLIT_CTL14::Register>),
30        (0x203C => amux_split_ctl_15: ReadWrite<u32, AMUX_SPLIT_CTL15::Register>),
31        (0x2040 => amux_split_ctl_16: ReadWrite<u32, AMUX_SPLIT_CTL16::Register>),
32        (0x2044 => amux_split_ctl_17: ReadWrite<u32, AMUX_SPLIT_CTL17::Register>),
33        (0x2048 => amux_split_ctl_18: ReadWrite<u32, AMUX_SPLIT_CTL18::Register>),
34        (0x204C => amux_split_ctl_19: ReadWrite<u32, AMUX_SPLIT_CTL19::Register>),
35        (0x2050 => amux_split_ctl_20: ReadWrite<u32, AMUX_SPLIT_CTL20::Register>),
36        (0x2054 => amux_split_ctl_21: ReadWrite<u32, AMUX_SPLIT_CTL21::Register>),
37        (0x2058 => amux_split_ctl_22: ReadWrite<u32, AMUX_SPLIT_CTL22::Register>),
38        (0x205C => amux_split_ctl_23: ReadWrite<u32, AMUX_SPLIT_CTL23::Register>),
39        (0x2060 => amux_split_ctl_24: ReadWrite<u32, AMUX_SPLIT_CTL24::Register>),
40        (0x2064 => amux_split_ctl_25: ReadWrite<u32, AMUX_SPLIT_CTL25::Register>),
41        (0x2068 => amux_split_ctl_26: ReadWrite<u32, AMUX_SPLIT_CTL26::Register>),
42        (0x206C => amux_split_ctl_27: ReadWrite<u32, AMUX_SPLIT_CTL27::Register>),
43        (0x2070 => amux_split_ctl_28: ReadWrite<u32, AMUX_SPLIT_CTL28::Register>),
44        (0x2074 => amux_split_ctl_29: ReadWrite<u32, AMUX_SPLIT_CTL29::Register>),
45        (0x2078 => amux_split_ctl_30: ReadWrite<u32, AMUX_SPLIT_CTL30::Register>),
46        (0x207C => amux_split_ctl_31: ReadWrite<u32, AMUX_SPLIT_CTL31::Register>),
47        (0x2080 => amux_split_ctl_32: ReadWrite<u32, AMUX_SPLIT_CTL32::Register>),
48        (0x2084 => amux_split_ctl_33: ReadWrite<u32, AMUX_SPLIT_CTL33::Register>),
49        (0x2088 => amux_split_ctl_34: ReadWrite<u32, AMUX_SPLIT_CTL34::Register>),
50        (0x208C => amux_split_ctl_35: ReadWrite<u32, AMUX_SPLIT_CTL35::Register>),
51        (0x2090 => amux_split_ctl_36: ReadWrite<u32, AMUX_SPLIT_CTL36::Register>),
52        (0x2094 => amux_split_ctl_37: ReadWrite<u32, AMUX_SPLIT_CTL37::Register>),
53        (0x2098 => amux_split_ctl_38: ReadWrite<u32, AMUX_SPLIT_CTL38::Register>),
54        (0x209C => amux_split_ctl_39: ReadWrite<u32, AMUX_SPLIT_CTL39::Register>),
55        (0x20A0 => amux_split_ctl_40: ReadWrite<u32, AMUX_SPLIT_CTL40::Register>),
56        (0x20A4 => amux_split_ctl_41: ReadWrite<u32, AMUX_SPLIT_CTL41::Register>),
57        (0x20A8 => amux_split_ctl_42: ReadWrite<u32, AMUX_SPLIT_CTL42::Register>),
58        (0x20AC => amux_split_ctl_43: ReadWrite<u32, AMUX_SPLIT_CTL43::Register>),
59        (0x20B0 => amux_split_ctl_44: ReadWrite<u32, AMUX_SPLIT_CTL44::Register>),
60        (0x20B4 => amux_split_ctl_45: ReadWrite<u32, AMUX_SPLIT_CTL45::Register>),
61        (0x20B8 => amux_split_ctl_46: ReadWrite<u32, AMUX_SPLIT_CTL46::Register>),
62        (0x20BC => amux_split_ctl_47: ReadWrite<u32, AMUX_SPLIT_CTL47::Register>),
63        (0x20C0 => amux_split_ctl_48: ReadWrite<u32, AMUX_SPLIT_CTL48::Register>),
64        (0x20C4 => amux_split_ctl_49: ReadWrite<u32, AMUX_SPLIT_CTL49::Register>),
65        (0x20C8 => amux_split_ctl_50: ReadWrite<u32, AMUX_SPLIT_CTL50::Register>),
66        (0x20CC => amux_split_ctl_51: ReadWrite<u32, AMUX_SPLIT_CTL51::Register>),
67        (0x20D0 => amux_split_ctl_52: ReadWrite<u32, AMUX_SPLIT_CTL52::Register>),
68        (0x20D4 => amux_split_ctl_53: ReadWrite<u32, AMUX_SPLIT_CTL53::Register>),
69        (0x20D8 => amux_split_ctl_54: ReadWrite<u32, AMUX_SPLIT_CTL54::Register>),
70        (0x20DC => amux_split_ctl_55: ReadWrite<u32, AMUX_SPLIT_CTL55::Register>),
71        (0x20E0 => amux_split_ctl_56: ReadWrite<u32, AMUX_SPLIT_CTL56::Register>),
72        (0x20E4 => amux_split_ctl_57: ReadWrite<u32, AMUX_SPLIT_CTL57::Register>),
73        (0x20E8 => amux_split_ctl_58: ReadWrite<u32, AMUX_SPLIT_CTL58::Register>),
74        (0x20EC => amux_split_ctl_59: ReadWrite<u32, AMUX_SPLIT_CTL59::Register>),
75        (0x20F0 => amux_split_ctl_60: ReadWrite<u32, AMUX_SPLIT_CTL60::Register>),
76        (0x20F4 => amux_split_ctl_61: ReadWrite<u32, AMUX_SPLIT_CTL61::Register>),
77        (0x20F8 => amux_split_ctl_62: ReadWrite<u32, AMUX_SPLIT_CTL62::Register>),
78        (0x20FC => amux_split_ctl_63: ReadWrite<u32, AMUX_SPLIT_CTL63::Register>),
79        (0x2100 => _reserved1),
80        (0x2200 => monitor_ctl_0: ReadWrite<u32>),
81        (0x2204 => monitor_ctl_1: ReadWrite<u32>),
82        (0x2208 => monitor_ctl_2: ReadWrite<u32>),
83        (0x220C => monitor_ctl_3: ReadWrite<u32>),
84        (0x2210 => _reserved2),
85        (0x2240 => alt_jtag_en: ReadWrite<u32>),
86        (0x2244 => @END),
87    }
88}
89register_bitfields![u32,
90PRT5_PORT_SEL0 [
91    IO0_SEL OFFSET(0) NUMBITS(5) [],
92    IO1_SEL OFFSET(8) NUMBITS(5) [],
93    IO2_SEL OFFSET(16) NUMBITS(5) [],
94],
95MONITOR_CTL_0 [
96    MONITOR_EN OFFSET(0) NUMBITS(32) []
97],
98MONITOR_CTL_1 [
99    MONITOR_EN OFFSET(0) NUMBITS(32) []
100],
101MONITOR_CTL_2 [
102    MONITOR_EN OFFSET(0) NUMBITS(32) []
103],
104MONITOR_CTL_3 [
105    MONITOR_EN OFFSET(0) NUMBITS(32) []
106],
107ALT_JTAG_EN [
108    ENABLE OFFSET(31) NUMBITS(1) []
109],
110AMUX_SPLIT_CTL0 [
111    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
112    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
113    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
114    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
115    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
116    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
117],
118AMUX_SPLIT_CTL1 [
119    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
120    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
121    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
122    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
123    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
124    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
125],
126AMUX_SPLIT_CTL2 [
127    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
128    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
129    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
130    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
131    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
132    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
133],
134AMUX_SPLIT_CTL3 [
135    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
136    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
137    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
138    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
139    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
140    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
141],
142AMUX_SPLIT_CTL4 [
143    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
144    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
145    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
146    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
147    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
148    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
149],
150AMUX_SPLIT_CTL5 [
151    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
152    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
153    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
154    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
155    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
156    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
157],
158AMUX_SPLIT_CTL6 [
159    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
160    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
161    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
162    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
163    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
164    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
165],
166AMUX_SPLIT_CTL7 [
167    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
168    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
169    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
170    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
171    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
172    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
173],
174AMUX_SPLIT_CTL8 [
175    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
176    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
177    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
178    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
179    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
180    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
181],
182AMUX_SPLIT_CTL9 [
183    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
184    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
185    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
186    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
187    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
188    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
189],
190AMUX_SPLIT_CTL10 [
191    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
192    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
193    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
194    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
195    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
196    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
197],
198AMUX_SPLIT_CTL11 [
199    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
200    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
201    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
202    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
203    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
204    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
205],
206AMUX_SPLIT_CTL12 [
207    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
208    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
209    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
210    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
211    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
212    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
213],
214AMUX_SPLIT_CTL13 [
215    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
216    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
217    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
218    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
219    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
220    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
221],
222AMUX_SPLIT_CTL14 [
223    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
224    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
225    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
226    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
227    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
228    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
229],
230AMUX_SPLIT_CTL15 [
231    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
232    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
233    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
234    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
235    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
236    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
237],
238AMUX_SPLIT_CTL16 [
239    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
240    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
241    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
242    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
243    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
244    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
245],
246AMUX_SPLIT_CTL17 [
247    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
248    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
249    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
250    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
251    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
252    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
253],
254AMUX_SPLIT_CTL18 [
255    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
256    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
257    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
258    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
259    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
260    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
261],
262AMUX_SPLIT_CTL19 [
263    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
264    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
265    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
266    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
267    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
268    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
269],
270AMUX_SPLIT_CTL20 [
271    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
272    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
273    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
274    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
275    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
276    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
277],
278AMUX_SPLIT_CTL21 [
279    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
280    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
281    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
282    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
283    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
284    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
285],
286AMUX_SPLIT_CTL22 [
287    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
288    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
289    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
290    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
291    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
292    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
293],
294AMUX_SPLIT_CTL23 [
295    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
296    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
297    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
298    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
299    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
300    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
301],
302AMUX_SPLIT_CTL24 [
303    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
304    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
305    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
306    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
307    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
308    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
309],
310AMUX_SPLIT_CTL25 [
311    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
312    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
313    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
314    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
315    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
316    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
317],
318AMUX_SPLIT_CTL26 [
319    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
320    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
321    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
322    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
323    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
324    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
325],
326AMUX_SPLIT_CTL27 [
327    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
328    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
329    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
330    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
331    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
332    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
333],
334AMUX_SPLIT_CTL28 [
335    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
336    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
337    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
338    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
339    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
340    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
341],
342AMUX_SPLIT_CTL29 [
343    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
344    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
345    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
346    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
347    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
348    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
349],
350AMUX_SPLIT_CTL30 [
351    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
352    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
353    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
354    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
355    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
356    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
357],
358AMUX_SPLIT_CTL31 [
359    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
360    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
361    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
362    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
363    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
364    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
365],
366AMUX_SPLIT_CTL32 [
367    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
368    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
369    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
370    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
371    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
372    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
373],
374AMUX_SPLIT_CTL33 [
375    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
376    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
377    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
378    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
379    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
380    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
381],
382AMUX_SPLIT_CTL34 [
383    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
384    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
385    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
386    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
387    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
388    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
389],
390AMUX_SPLIT_CTL35 [
391    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
392    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
393    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
394    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
395    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
396    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
397],
398AMUX_SPLIT_CTL36 [
399    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
400    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
401    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
402    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
403    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
404    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
405],
406AMUX_SPLIT_CTL37 [
407    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
408    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
409    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
410    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
411    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
412    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
413],
414AMUX_SPLIT_CTL38 [
415    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
416    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
417    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
418    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
419    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
420    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
421],
422AMUX_SPLIT_CTL39 [
423    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
424    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
425    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
426    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
427    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
428    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
429],
430AMUX_SPLIT_CTL40 [
431    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
432    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
433    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
434    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
435    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
436    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
437],
438AMUX_SPLIT_CTL41 [
439    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
440    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
441    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
442    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
443    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
444    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
445],
446AMUX_SPLIT_CTL42 [
447    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
448    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
449    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
450    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
451    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
452    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
453],
454AMUX_SPLIT_CTL43 [
455    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
456    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
457    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
458    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
459    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
460    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
461],
462AMUX_SPLIT_CTL44 [
463    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
464    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
465    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
466    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
467    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
468    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
469],
470AMUX_SPLIT_CTL45 [
471    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
472    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
473    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
474    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
475    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
476    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
477],
478AMUX_SPLIT_CTL46 [
479    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
480    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
481    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
482    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
483    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
484    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
485],
486AMUX_SPLIT_CTL47 [
487    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
488    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
489    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
490    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
491    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
492    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
493],
494AMUX_SPLIT_CTL48 [
495    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
496    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
497    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
498    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
499    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
500    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
501],
502AMUX_SPLIT_CTL49 [
503    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
504    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
505    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
506    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
507    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
508    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
509],
510AMUX_SPLIT_CTL50 [
511    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
512    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
513    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
514    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
515    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
516    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
517],
518AMUX_SPLIT_CTL51 [
519    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
520    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
521    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
522    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
523    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
524    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
525],
526AMUX_SPLIT_CTL52 [
527    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
528    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
529    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
530    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
531    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
532    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
533],
534AMUX_SPLIT_CTL53 [
535    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
536    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
537    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
538    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
539    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
540    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
541],
542AMUX_SPLIT_CTL54 [
543    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
544    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
545    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
546    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
547    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
548    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
549],
550AMUX_SPLIT_CTL55 [
551    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
552    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
553    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
554    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
555    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
556    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
557],
558AMUX_SPLIT_CTL56 [
559    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
560    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
561    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
562    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
563    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
564    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
565],
566AMUX_SPLIT_CTL57 [
567    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
568    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
569    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
570    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
571    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
572    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
573],
574AMUX_SPLIT_CTL58 [
575    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
576    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
577    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
578    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
579    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
580    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
581],
582AMUX_SPLIT_CTL59 [
583    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
584    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
585    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
586    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
587    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
588    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
589],
590AMUX_SPLIT_CTL60 [
591    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
592    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
593    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
594    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
595    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
596    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
597],
598AMUX_SPLIT_CTL61 [
599    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
600    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
601    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
602    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
603    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
604    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
605],
606AMUX_SPLIT_CTL62 [
607    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
608    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
609    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
610    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
611    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
612    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
613],
614AMUX_SPLIT_CTL63 [
615    SWITCH_AA_SL OFFSET(0) NUMBITS(1) [],
616    SWITCH_AA_SR OFFSET(1) NUMBITS(1) [],
617    SWITCH_AA_S0 OFFSET(2) NUMBITS(1) [],
618    SWITCH_BB_SL OFFSET(4) NUMBITS(1) [],
619    SWITCH_BB_SR OFFSET(5) NUMBITS(1) [],
620    SWITCH_BB_S0 OFFSET(6) NUMBITS(1) []
621]
622];
623const HSIOM_BASE: StaticRef<HsiomRegisters> =
624    unsafe { StaticRef::new(0x40300000 as *const HsiomRegisters) };
625
626pub struct Hsiom {
627    registers: StaticRef<HsiomRegisters>,
628}
629
630impl Hsiom {
631    pub const fn new() -> Hsiom {
632        Hsiom {
633            registers: HSIOM_BASE,
634        }
635    }
636
637    pub fn enable_uart(&self) {
638        self.registers
639            .prt5_port_sel0
640            .modify(PRT5_PORT_SEL0::IO1_SEL.val(0x12));
641        self.registers
642            .prt5_port_sel0
643            .modify(PRT5_PORT_SEL0::IO0_SEL.val(0x12));
644    }
645}
psoc62xa/hsiom.rs

psoc62xa/
hsiom.rs
