lowrisc/registers/
rv_timer_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for rv_timer.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/rv_timer/data/rv_timer.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of harts
15pub const RV_TIMER_PARAM_N_HARTS: u32 = 1;
16/// Number of timers per Hart
17pub const RV_TIMER_PARAM_N_TIMERS: u32 = 1;
18/// Number of alerts
19pub const RV_TIMER_PARAM_NUM_ALERTS: u32 = 1;
20/// Register width
21pub const RV_TIMER_PARAM_REG_WIDTH: u32 = 32;
22
23register_structs! {
24    pub RvTimerRegisters {
25        /// Alert Test Register
26        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
27        /// Control register
28        (0x0004 => pub(crate) ctrl: [ReadWrite<u32, CTRL::Register>; 1]),
29        (0x0008 => _reserved1),
30        /// Interrupt Enable
31        (0x0100 => pub(crate) intr_enable0: [ReadWrite<u32, INTR_ENABLE0::Register>; 1]),
32        /// Interrupt Status
33        (0x0104 => pub(crate) intr_state0: [ReadWrite<u32, INTR_STATE0::Register>; 1]),
34        /// Interrupt test register
35        (0x0108 => pub(crate) intr_test0: [ReadWrite<u32, INTR_TEST0::Register>; 1]),
36        /// Configuration for Hart 0
37        (0x010c => pub(crate) cfg0: ReadWrite<u32, CFG0::Register>),
38        /// Timer value Lower
39        (0x0110 => pub(crate) timer_v_lower0: ReadWrite<u32, TIMER_V_LOWER0::Register>),
40        /// Timer value Upper
41        (0x0114 => pub(crate) timer_v_upper0: ReadWrite<u32, TIMER_V_UPPER0::Register>),
42        /// Timer value Lower
43        (0x0118 => pub(crate) compare_lower0_0: ReadWrite<u32, COMPARE_LOWER0_0::Register>),
44        /// Timer value Upper
45        (0x011c => pub(crate) compare_upper0_0: ReadWrite<u32, COMPARE_UPPER0_0::Register>),
46        (0x0120 => @END),
47    }
48}
49
50register_bitfields![u32,
51    pub(crate) ALERT_TEST [
52        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
53    ],
54    pub(crate) CTRL [
55        ACTIVE_0 OFFSET(0) NUMBITS(1) [],
56    ],
57    pub(crate) INTR_ENABLE0 [
58        IE_0 OFFSET(0) NUMBITS(1) [],
59    ],
60    pub(crate) INTR_STATE0 [
61        IS_0 OFFSET(0) NUMBITS(1) [],
62    ],
63    pub(crate) INTR_TEST0 [
64        T_0 OFFSET(0) NUMBITS(1) [],
65    ],
66    pub(crate) CFG0 [
67        PRESCALE OFFSET(0) NUMBITS(12) [],
68        STEP OFFSET(16) NUMBITS(8) [],
69    ],
70    pub(crate) TIMER_V_LOWER0 [
71        V OFFSET(0) NUMBITS(32) [],
72    ],
73    pub(crate) TIMER_V_UPPER0 [
74        V OFFSET(0) NUMBITS(32) [],
75    ],
76    pub(crate) COMPARE_LOWER0_0 [
77        V OFFSET(0) NUMBITS(32) [],
78    ],
79    pub(crate) COMPARE_UPPER0_0 [
80        V OFFSET(0) NUMBITS(32) [],
81    ],
82];
83
84// End generated register constants for rv_timer
lowrisc/registers/rv_timer_regs.rs

lowrisc/registers/
rv_timer_regs.rs
