lowrisc/registers/
clkmgr_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for clkmgr.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/clkmgr/data/clkmgr.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of clock groups
15pub const CLKMGR_PARAM_NUM_GROUPS: u32 = 7;
16/// Register width
17pub const CLKMGR_PARAM_REG_WIDTH: u32 = 32;
18
19register_structs! {
20    pub ClkmgrRegisters {
21        /// Clock enable for software gateable clocks.
22        (0x0000 => pub(crate) clk_enables: ReadWrite<u32, CLK_ENABLES::Register>),
23        /// Clock hint for software gateable clocks.
24        (0x0004 => pub(crate) clk_hints: ReadWrite<u32, CLK_HINTS::Register>),
25        /// Since the final state of !!CLK_HINTS is not always determined by software,
26        (0x0008 => pub(crate) clk_hints_status: ReadWrite<u32, CLK_HINTS_STATUS::Register>),
27        (0x000c => @END),
28    }
29}
30
31register_bitfields![u32,
32    pub(crate) CLK_ENABLES [
33        CLK_FIXED_PERI_EN OFFSET(0) NUMBITS(1) [],
34        CLK_USB_48MHZ_PERI_EN OFFSET(1) NUMBITS(1) [],
35    ],
36    pub(crate) CLK_HINTS [
37        CLK_MAIN_AES_HINT OFFSET(0) NUMBITS(1) [],
38        CLK_MAIN_HMAC_HINT OFFSET(1) NUMBITS(1) [],
39    ],
40    pub(crate) CLK_HINTS_STATUS [
41        CLK_MAIN_AES_VAL OFFSET(0) NUMBITS(1) [],
42        CLK_MAIN_HMAC_VAL OFFSET(1) NUMBITS(1) [],
43    ],
44];
45
46// End generated register constants for clkmgr
lowrisc/registers/clkmgr_regs.rs

lowrisc/registers/
clkmgr_regs.rs
