lowrisc/registers/
aes_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for aes.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/ip/aes/data/aes.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number registers for key
15pub const AES_PARAM_NUM_REGS_KEY: u32 = 8;
16/// Number registers for initialization vector
17pub const AES_PARAM_NUM_REGS_IV: u32 = 4;
18/// Number registers for input and output data
19pub const AES_PARAM_NUM_REGS_DATA: u32 = 4;
20/// Number of alerts
21pub const AES_PARAM_NUM_ALERTS: u32 = 2;
22/// Register width
23pub const AES_PARAM_REG_WIDTH: u32 = 32;
24
25register_structs! {
26    pub AesRegisters {
27        /// Alert Test Register
28        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
29        /// Initial Key Registers Share 0.
30        (0x0004 => pub(crate) key_share0: [ReadWrite<u32, KEY_SHARE0::Register>; 8]),
31        /// Initial Key Registers Share 1.
32        (0x0024 => pub(crate) key_share1: [ReadWrite<u32, KEY_SHARE1::Register>; 8]),
33        /// Initialization Vector Registers.
34        (0x0044 => pub(crate) iv: [ReadWrite<u32, IV::Register>; 4]),
35        /// Input Data Registers.
36        (0x0054 => pub(crate) data_in: [ReadWrite<u32, DATA_IN::Register>; 4]),
37        /// Output Data Register.
38        (0x0064 => pub(crate) data_out: [ReadWrite<u32, DATA_OUT::Register>; 4]),
39        /// Control Register.
40        (0x0074 => pub(crate) ctrl_shadowed: ReadWrite<u32, CTRL_SHADOWED::Register>),
41        /// Auxiliary Control Register.
42        (0x0078 => pub(crate) ctrl_aux_shadowed: ReadWrite<u32, CTRL_AUX_SHADOWED::Register>),
43        /// Lock bit for Auxiliary Control Register.
44        (0x007c => pub(crate) ctrl_aux_regwen: ReadWrite<u32, CTRL_AUX_REGWEN::Register>),
45        /// Trigger Register.
46        (0x0080 => pub(crate) trigger: ReadWrite<u32, TRIGGER::Register>),
47        /// Status Register
48        (0x0084 => pub(crate) status: ReadWrite<u32, STATUS::Register>),
49        (0x0088 => @END),
50    }
51}
52
53register_bitfields![u32,
54    pub(crate) ALERT_TEST [
55        RECOV_CTRL_UPDATE_ERR OFFSET(0) NUMBITS(1) [],
56        FATAL_FAULT OFFSET(1) NUMBITS(1) [],
57    ],
58    pub(crate) KEY_SHARE0 [
59        KEY_SHARE0_0 OFFSET(0) NUMBITS(32) [],
60    ],
61    pub(crate) KEY_SHARE1 [
62        KEY_SHARE1_0 OFFSET(0) NUMBITS(32) [],
63    ],
64    pub(crate) IV [
65        IV_0 OFFSET(0) NUMBITS(32) [],
66    ],
67    pub(crate) DATA_IN [
68        DATA_IN_0 OFFSET(0) NUMBITS(32) [],
69    ],
70    pub(crate) DATA_OUT [
71        DATA_OUT_0 OFFSET(0) NUMBITS(32) [],
72    ],
73    pub(crate) CTRL_SHADOWED [
74        OPERATION OFFSET(0) NUMBITS(2) [
75            AES_ENC = 1,
76            AES_DEC = 2,
77        ],
78        MODE OFFSET(2) NUMBITS(6) [
79            AES_ECB = 1,
80            AES_CBC = 2,
81            AES_CFB = 4,
82            AES_OFB = 8,
83            AES_CTR = 16,
84            AES_NONE = 32,
85        ],
86        KEY_LEN OFFSET(8) NUMBITS(3) [
87            AES_128 = 1,
88            AES_192 = 2,
89            AES_256 = 4,
90        ],
91        SIDELOAD OFFSET(11) NUMBITS(1) [],
92        PRNG_RESEED_RATE OFFSET(12) NUMBITS(3) [
93            PER_1 = 1,
94            PER_64 = 2,
95            PER_8K = 4,
96        ],
97        MANUAL_OPERATION OFFSET(15) NUMBITS(1) [],
98    ],
99    pub(crate) CTRL_AUX_SHADOWED [
100        KEY_TOUCH_FORCES_RESEED OFFSET(0) NUMBITS(1) [],
101        FORCE_MASKS OFFSET(1) NUMBITS(1) [],
102    ],
103    pub(crate) CTRL_AUX_REGWEN [
104        CTRL_AUX_REGWEN OFFSET(0) NUMBITS(1) [],
105    ],
106    pub(crate) TRIGGER [
107        START OFFSET(0) NUMBITS(1) [],
108        KEY_IV_DATA_IN_CLEAR OFFSET(1) NUMBITS(1) [],
109        DATA_OUT_CLEAR OFFSET(2) NUMBITS(1) [],
110        PRNG_RESEED OFFSET(3) NUMBITS(1) [],
111    ],
112    pub(crate) STATUS [
113        IDLE OFFSET(0) NUMBITS(1) [],
114        STALL OFFSET(1) NUMBITS(1) [],
115        OUTPUT_LOST OFFSET(2) NUMBITS(1) [],
116        OUTPUT_VALID OFFSET(3) NUMBITS(1) [],
117        INPUT_READY OFFSET(4) NUMBITS(1) [],
118        ALERT_RECOV_CTRL_UPDATE_ERR OFFSET(5) NUMBITS(1) [],
119        ALERT_FATAL_FAULT OFFSET(6) NUMBITS(1) [],
120    ],
121];
122
123// End generated register constants for aes
lowrisc/registers/aes_regs.rs

lowrisc/registers/
aes_regs.rs
