imxrt10xx/
iomuxc_snvs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2022.
4
5use crate::iomuxc::{DriveStrength, MuxMode, OpenDrainEn, PullKeepEn, PullUpDown, Sion, Speed};
6use kernel::utilities::registers::interfaces::{ReadWriteable, Readable};
7use kernel::utilities::registers::{register_bitfields, ReadWrite};
8use kernel::utilities::StaticRef;
9
10/// IOMUX SNVS Controller Module
11#[repr(C)]
12struct IomuxcSnvsRegisters {
13    sw_mux_ctl_pad_wakeup: ReadWrite<u32, SW_MUX_CTL_PAD_WAKEUP::Register>,
14    sw_mux_ctl_pad_pmic_on_req: ReadWrite<u32, SW_MUX_CTL_PAD_PMIC_ON_REQ::Register>,
15    sw_mux_ctl_pad_pmic_stby_req: ReadWrite<u32, SW_MUX_CTL_PAD_PMIC_STBY_REQ::Register>,
16    sw_pad_ctl_pad_test_mode: ReadWrite<u32, SW_PAD_CTL_PAD_TEST_MODE::Register>,
17    sw_pad_ctl_pad_por_b: ReadWrite<u32, SW_PAD_CTL_PAD_POR_B::Register>,
18    sw_pad_ctl_pad_onoff: ReadWrite<u32, SW_PAD_CTL_PAD_ONOFF::Register>,
19    sw_pad_ctl_pad_wakeup: ReadWrite<u32, SW_PAD_CTL_PAD_WAKEUP::Register>,
20    sw_pad_ctl_pad_pmic_on_req: ReadWrite<u32, SW_PAD_CTL_PAD_PMIC_ON_REQ::Register>,
21    sw_pad_ctl_pad_pmic_stby_req: ReadWrite<u32, SW_PAD_CTL_PAD_PMIC_STBY_REQ::Register>,
22}
23
24register_bitfields![u32,
25    SW_MUX_CTL_PAD_WAKEUP [
26        // Software Input On Field
27        SION OFFSET(4) NUMBITS(1) [],
28        // MUX Mode Select Field
29        MUX_MODE OFFSET(0) NUMBITS(3) []
30    ],
31
32    SW_MUX_CTL_PAD_PMIC_ON_REQ [
33        // Software Input On Field
34        SION OFFSET(4) NUMBITS(1) [],
35        // MUX Mode Select Field
36        MUX_MODE OFFSET(0) NUMBITS(3) []
37    ],
38
39    SW_MUX_CTL_PAD_PMIC_STBY_REQ [
40        // Software Input On Field
41        SION OFFSET(4) NUMBITS(1) [],
42        // MUX Mode Select Field
43        MUX_MODE OFFSET(0) NUMBITS(3) []
44    ],
45
46    SW_PAD_CTL_PAD_TEST_MODE [
47        // Hyst. Enable Field
48        HYS OFFSET(16) NUMBITS(1) [],
49        // Pull Up / Down Config Field
50        PUS OFFSET(14) NUMBITS(2) [],
51        // Pull / Keep Select Field
52        PUE OFFSET(13) NUMBITS(1) [],
53        // Pull / Keep enable field
54        PKE OFFSET(12) NUMBITS(1) [],
55        // Open drain enable field
56        ODE OFFSET(11) NUMBITS(1) [],
57        // Speed
58        SPEED OFFSET(6) NUMBITS(2) [],
59        // Drive Strength Field
60        DSE OFFSET(3) NUMBITS(3) [],
61        // Slew Rate Field
62        SRE OFFSET(0) NUMBITS(1) []
63    ],
64
65    SW_PAD_CTL_PAD_POR_B [
66        // Hyst. Enable Field
67        HYS OFFSET(16) NUMBITS(1) [],
68        // Pull Up / Down Config Field
69        PUS OFFSET(14) NUMBITS(2) [],
70        // Pull / Keep Select Field
71        PUE OFFSET(13) NUMBITS(1) [],
72        // Pull / Keep enable field
73        PKE OFFSET(12) NUMBITS(1) [],
74        // Open drain enable field
75        ODE OFFSET(11) NUMBITS(1) [],
76        // Speed
77        SPEED OFFSET(6) NUMBITS(2) [],
78        // Drive Strength Field
79        DSE OFFSET(3) NUMBITS(3) [],
80        // Slew Rate Field
81        SRE OFFSET(0) NUMBITS(1) []
82    ],
83
84    SW_PAD_CTL_PAD_ONOFF [
85        // Hyst. Enable Field
86        HYS OFFSET(16) NUMBITS(1) [],
87        // Pull Up / Down Config Field
88        PUS OFFSET(14) NUMBITS(2) [],
89        // Pull / Keep Select Field
90        PUE OFFSET(13) NUMBITS(1) [],
91        // Pull / Keep enable field
92        PKE OFFSET(12) NUMBITS(1) [],
93        // Open drain enable field
94        ODE OFFSET(11) NUMBITS(1) [],
95        // Speed
96        SPEED OFFSET(6) NUMBITS(2) [],
97        // Drive Strength Field
98        DSE OFFSET(3) NUMBITS(3) [],
99        // Slew Rate Field
100        SRE OFFSET(0) NUMBITS(1) []
101    ],
102
103    SW_PAD_CTL_PAD_WAKEUP [
104        // Hyst. Enable Field
105        HYS OFFSET(16) NUMBITS(1) [],
106        // Pull Up / Down Config Field
107        PUS OFFSET(14) NUMBITS(2) [],
108        // Pull / Keep Select Field
109        PUE OFFSET(13) NUMBITS(1) [],
110        // Pull / Keep enable field
111        PKE OFFSET(12) NUMBITS(1) [],
112        // Open drain enable field
113        ODE OFFSET(11) NUMBITS(1) [],
114        // Speed
115        SPEED OFFSET(6) NUMBITS(2) [],
116        // Drive Strength Field
117        DSE OFFSET(3) NUMBITS(3) [],
118        // Slew Rate Field
119        SRE OFFSET(0) NUMBITS(1) []
120    ],
121
122    SW_PAD_CTL_PAD_PMIC_ON_REQ [
123        // Hyst. Enable Field
124        HYS OFFSET(16) NUMBITS(1) [],
125        // Pull Up / Down Config Field
126        PUS OFFSET(14) NUMBITS(2) [],
127        // Pull / Keep Select Field
128        PUE OFFSET(13) NUMBITS(1) [],
129        // Pull / Keep enable field
130        PKE OFFSET(12) NUMBITS(1) [],
131        // Open drain enable field
132        ODE OFFSET(11) NUMBITS(1) [],
133        // Speed
134        SPEED OFFSET(6) NUMBITS(2) [],
135        // Drive Strength Field
136        DSE OFFSET(3) NUMBITS(3) [],
137        // Slew Rate Field
138        SRE OFFSET(0) NUMBITS(1) []
139    ],
140
141    SW_PAD_CTL_PAD_PMIC_STBY_REQ [
142        // Hyst. Enable Field
143        HYS OFFSET(16) NUMBITS(1) [],
144        // Pull Up / Down Config Field
145        PUS OFFSET(14) NUMBITS(2) [],
146        // Pull / Keep Select Field
147        PUE OFFSET(13) NUMBITS(1) [],
148        // Pull / Keep enable field
149        PKE OFFSET(12) NUMBITS(1) [],
150        // Open drain enable field
151        ODE OFFSET(11) NUMBITS(1) [],
152        // Speed
153        SPEED OFFSET(6) NUMBITS(2) [],
154        // Drive Strength Field
155        DSE OFFSET(3) NUMBITS(3) [],
156        // Slew Rate Field
157        SRE OFFSET(0) NUMBITS(1) []
158    ]
159
160];
161
162const IOMUXC_SNVS_BASE: StaticRef<IomuxcSnvsRegisters> =
163    unsafe { StaticRef::new(0x400A8000 as *const IomuxcSnvsRegisters) };
164
165pub struct IomuxcSnvs {
166    registers: StaticRef<IomuxcSnvsRegisters>,
167}
168
169impl IomuxcSnvs {
170    pub const fn new() -> IomuxcSnvs {
171        IomuxcSnvs {
172            registers: IOMUXC_SNVS_BASE,
173        }
174    }
175
176    pub fn is_enabled_sw_mux_ctl_pad_gpio_mode(&self, pin: usize) -> bool {
177        match pin {
178            0 => self
179                .registers
180                .sw_mux_ctl_pad_wakeup
181                .is_set(SW_MUX_CTL_PAD_WAKEUP::MUX_MODE),
182            1 => self
183                .registers
184                .sw_mux_ctl_pad_pmic_on_req
185                .is_set(SW_MUX_CTL_PAD_PMIC_ON_REQ::MUX_MODE),
186            2 => self
187                .registers
188                .sw_mux_ctl_pad_pmic_stby_req
189                .is_set(SW_MUX_CTL_PAD_PMIC_STBY_REQ::MUX_MODE),
190            _ => false,
191        }
192    }
193
194    pub fn enable_sw_mux_ctl_pad_gpio(&self, mode: MuxMode, sion: Sion, pin: usize) {
195        match pin {
196            0 => {
197                self.registers.sw_mux_ctl_pad_wakeup.modify(
198                    SW_MUX_CTL_PAD_WAKEUP::MUX_MODE.val(mode as u32)
199                        + SW_MUX_CTL_PAD_WAKEUP::SION.val(sion as u32),
200                );
201            }
202            1 => {
203                self.registers.sw_mux_ctl_pad_pmic_on_req.modify(
204                    SW_MUX_CTL_PAD_PMIC_ON_REQ::MUX_MODE.val(mode as u32)
205                        + SW_MUX_CTL_PAD_PMIC_ON_REQ::SION.val(sion as u32),
206                );
207            }
208            2 => {
209                self.registers.sw_mux_ctl_pad_pmic_stby_req.modify(
210                    SW_MUX_CTL_PAD_PMIC_STBY_REQ::MUX_MODE.val(mode as u32)
211                        + SW_MUX_CTL_PAD_PMIC_STBY_REQ::SION.val(sion as u32),
212                );
213            }
214            _ => {}
215        }
216    }
217
218    pub fn disable_sw_mux_ctl_pad_gpio(&self, pin: usize) {
219        match pin {
220            0 => {
221                self.registers.sw_mux_ctl_pad_wakeup.modify(
222                    SW_MUX_CTL_PAD_WAKEUP::MUX_MODE::CLEAR + SW_MUX_CTL_PAD_WAKEUP::SION::CLEAR,
223                );
224            }
225            1 => {
226                self.registers.sw_mux_ctl_pad_pmic_on_req.modify(
227                    SW_MUX_CTL_PAD_PMIC_ON_REQ::MUX_MODE::CLEAR
228                        + SW_MUX_CTL_PAD_PMIC_ON_REQ::SION::CLEAR,
229                );
230            }
231            2 => {
232                self.registers.sw_mux_ctl_pad_pmic_stby_req.modify(
233                    SW_MUX_CTL_PAD_PMIC_STBY_REQ::MUX_MODE::CLEAR
234                        + SW_MUX_CTL_PAD_PMIC_STBY_REQ::SION::CLEAR,
235                );
236            }
237            _ => {}
238        }
239    }
240
241    pub fn configure_sw_pad_ctl_pad_gpio(
242        &self,
243        pin: usize,
244        pus: PullUpDown,
245        pke: PullKeepEn,
246        ode: OpenDrainEn,
247        speed: Speed,
248        dse: DriveStrength,
249    ) {
250        match pin {
251            0 => {
252                self.registers.sw_pad_ctl_pad_wakeup.modify(
253                    SW_PAD_CTL_PAD_WAKEUP::PUS.val(pus as u32)
254                        + SW_PAD_CTL_PAD_WAKEUP::PKE.val(pke as u32)
255                        + SW_PAD_CTL_PAD_WAKEUP::ODE.val(ode as u32)
256                        + SW_PAD_CTL_PAD_WAKEUP::SPEED.val(speed as u32)
257                        + SW_PAD_CTL_PAD_WAKEUP::DSE.val(dse as u32),
258                );
259            }
260            1 => {
261                self.registers.sw_pad_ctl_pad_pmic_on_req.modify(
262                    SW_PAD_CTL_PAD_PMIC_ON_REQ::PUS.val(pus as u32)
263                        + SW_PAD_CTL_PAD_PMIC_ON_REQ::PKE.val(pke as u32)
264                        + SW_PAD_CTL_PAD_PMIC_ON_REQ::ODE.val(ode as u32)
265                        + SW_PAD_CTL_PAD_PMIC_ON_REQ::SPEED.val(speed as u32)
266                        + SW_PAD_CTL_PAD_PMIC_ON_REQ::DSE.val(dse as u32),
267                );
268            }
269            2 => {
270                self.registers.sw_pad_ctl_pad_pmic_stby_req.modify(
271                    SW_PAD_CTL_PAD_PMIC_STBY_REQ::PUS.val(pus as u32)
272                        + SW_PAD_CTL_PAD_PMIC_STBY_REQ::PKE.val(pke as u32)
273                        + SW_PAD_CTL_PAD_PMIC_STBY_REQ::ODE.val(ode as u32)
274                        + SW_PAD_CTL_PAD_PMIC_STBY_REQ::SPEED.val(speed as u32)
275                        + SW_PAD_CTL_PAD_PMIC_STBY_REQ::DSE.val(dse as u32),
276                );
277            }
278            _ => {}
279        }
280    }
281}
imxrt10xx/iomuxc_snvs.rs

imxrt10xx/
iomuxc_snvs.rs
