earlgrey_cw310/pinmux_layout.rs
1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright Tock Contributors 2023.
4
5use earlgrey::pinmux_config::{EarlGreyPinmuxConfig, INPUT_NUM, OUTPUT_NUM};
6use earlgrey::registers::top_earlgrey::{PinmuxInsel, PinmuxOutsel};
7
8type In = PinmuxInsel;
9type Out = PinmuxOutsel;
10
11/// Pinmux configuration for hyperdebug with cw310.
12///
13/// The primary reference for this config is:
14/// <OPENTITAN_TREE>/hw/top_earlgrey/data/pins_cw310_hyperdebug.xdc
15/// pins_cw310_hyperdebug.xdc sometimes underspecifies the layout
16/// (e.g. it doesn't indicate UART numbering); we resolve the
17/// ambiguity by using
18/// <OPENTITAN_TREE>/hw/top_earlgrey/data/pins_cw310.xdc
19pub enum BoardPinmuxLayout {}
20
21impl EarlGreyPinmuxConfig for BoardPinmuxLayout {
22 #[rustfmt::skip]
23 const INPUT: &'static [PinmuxInsel; INPUT_NUM] = &[
24 In::Ioa2, // GpioGpio0
25 In::Ioa3, // GpioGpio1
26 In::Ioa6, // GpioGpio2
27 In::Iob0, // GpioGpio3
28 In::Iob1, // GpioGpio4
29 In::Iob2, // GpioGpio5
30 In::Iob3, // GpioGpio6
31 In::Iob6, // GpioGpio7
32 In::Iob7, // GpioGpio8
33 In::Iob8, // GpioGpio9
34 In::Ioc0, // GpioGpio10
35 In::Ioc1, // GpioGpio11
36 In::Ioc2, // GpioGpio12
37 In::Ioc5, // GpioGpio13
38 In::Ioc6, // GpioGpio14
39 In::Ioc7, // GpioGpio15
40 In::Ioc8, // GpioGpio16
41 In::Ioc9, // GpioGpio17
42 In::Ioc10, // GpioGpio18
43 In::Ioc11, // GpioGpio19
44 In::Ioc12, // GpioGpio20
45 In::Ior0, // GpioGpio21
46 In::Ior1, // GpioGpio22
47 In::Ior2, // GpioGpio23
48 In::Ior3, // GpioGpio24
49 In::Ior4, // GpioGpio25
50 In::Ior5, // GpioGpio26
51 In::Ior6, // GpioGpio27
52 In::Ior7, // GpioGpio28
53 In::Ior10, // GpioGpio29
54 In::Ior11, // GpioGpio30
55 In::Ior12, // GpioGpio31
56 In::Iob12, // I2c0Sda
57 In::Iob11, // I2c0Scl
58 In::Ioa7, // I2c1Sda
59 In::Ioa8, // I2c1Scl
60 In::Iob9, // I2c2Sda
61 In::Iob10, // I2c2Scl
62 In::ConstantZero, // SpiHost1Sd0
63 In::ConstantZero, // SpiHost1Sd1
64 In::ConstantZero, // SpiHost1Sd2
65 In::ConstantZero, // SpiHost1Sd3
66 In::Ioc3, // Uart0Rx
67 In::Iob4, // Uart1Rx
68 In::Ioa0, // Uart2Rx
69 In::Ioa4, // Uart3Rx
70 In::ConstantZero, // SpiDeviceTpmCsb
71 In::ConstantZero, // FlashCtrlTck
72 In::ConstantZero, // FlashCtrlTms
73 In::ConstantZero, // FlashCtrlTdi
74 In::ConstantZero, // SysrstCtrlAonAcPresent
75 In::ConstantZero, // SysrstCtrlAonKey0In
76 In::ConstantZero, // SysrstCtrlAonKey1In
77 In::ConstantZero, // SysrstCtrlAonKey2In
78 In::ConstantZero, // SysrstCtrlAonPwrbIn
79 In::ConstantZero, // SysrstCtrlAonLidOpen
80 In::ConstantZero, // UsbdevSense
81 ];
82
83 #[rustfmt::skip]
84 const OUTPUT: &'static [PinmuxOutsel; OUTPUT_NUM] = &[
85 // __________ BANK IOA __________
86 Out::ConstantHighZ, // Ioa0 UART2_RX
87 Out::Uart2Tx, // Ioa1 UART2_TX
88 Out::GpioGpio0, // Ioa2
89 Out::GpioGpio1, // Ioa3
90 Out::ConstantHighZ, // Ioa4 UART3_RX
91 Out::Uart3Tx, // Ioa5 UART3_TX
92 Out::GpioGpio2, // Ioa6
93 Out::I2c1Sda, // Ioa7 I2C1_SDA
94 Out::I2c1Scl, // Ioa8 I2C1_SCL
95 // __________ BANK IOB __________
96 Out::GpioGpio3, // Iob0 SPI_HOST_CS
97 Out::GpioGpio4, // Iob1 SPI_HOST_DI
98 Out::GpioGpio5, // Iob2 SPI_HOST_DO
99 Out::GpioGpio6, // Iob3 SPI_HOST_CLK
100 Out::ConstantHighZ, // Iob4 UART1_RX
101 Out::Uart1Tx, // Iob5 UART1_TX
102 Out::GpioGpio7, // Iob6
103 Out::GpioGpio8, // Iob7
104 Out::GpioGpio9, // Iob8
105 Out::I2c2Sda, // Iob9 I2C2_SDA
106 Out::I2c2Scl, // Iob10 I2C2_SCL
107 Out::I2c0Scl, // Iob11 I2C0_SCL
108 Out::I2c0Sda, // Iob12 I2C0_SDA
109 // __________ BANK IOC __________
110 Out::GpioGpio10, // Ioc0
111 Out::GpioGpio11, // Ioc1
112 Out::GpioGpio12, // Ioc2
113 Out::ConstantHighZ, // Ioc3 UART0_RX
114 Out::Uart0Tx, // Ioc4 UART0_TX
115 Out::ConstantHighZ, // Ioc5 (TAP STRAP 1)
116 Out::GpioGpio14, // Ioc6
117 Out::GpioGpio15, // Ioc7
118 Out::ConstantHighZ, // Ioc8 (TAP STRAP 0)
119 Out::GpioGpio17, // Ioc9
120 Out::GpioGpio18, // Ioc10
121 Out::GpioGpio19, // Ioc11
122 Out::GpioGpio20, // Ioc12
123 // __________ BANK IOR __________
124 Out::GpioGpio21, // Ior0
125 Out::GpioGpio22, // Ior1
126 Out::GpioGpio23, // Ior2
127 Out::GpioGpio24, // Ior3
128 Out::GpioGpio25, // Ior4
129 Out::GpioGpio26, // Ior5
130 Out::GpioGpio27, // Ior6
131 Out::GpioGpio28, // Ior7
132 // DIO CW310_hyp // Ior8
133 // DIO CW310_hyp // Ior9
134 Out::GpioGpio29, // Ior10
135 Out::GpioGpio30, // Ior11
136 Out::GpioGpio31, // Ior12
137 Out::ConstantHighZ, // Ior13
138 ];
139}