earlgrey/registers/

top_earlgrey.rs

// Licensed under the Apache License, Version 2.0 or the MIT License.
// SPDX-License-Identifier: Apache-2.0 OR MIT
// Copyright lowRISC contributors 2023.

// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
// Tree status: clean
// Build date: 2023-10-18T10:18:57.529279

// This file was generated automatically.
// Please do not modify content of this file directly.
// File generated by using template: "toplevel.rs.tpl"
// To regenerate this file follow OpenTitan topgen documentations.

#![allow(dead_code)]

//! This file contains enums and consts for use within the Rust codebase.
//!
//! These definitions are for information that depends on the top-specific chip
//! configuration, which includes:
//! - Device Memory Information (for Peripherals and Memory)
//! - PLIC Interrupt ID Names and Source Mappings
//! - Alert ID Names and Source Mappings
//! - Pinmux Pin/Select Names
//! - Power Manager Wakeups

/// Peripheral base address for uart0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const UART0_BASE_ADDR: usize = 0x40000000;

/// Peripheral size for uart0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #UART0_BASE_ADDR and
/// `UART0_BASE_ADDR + UART0_SIZE_BYTES`.
pub const UART0_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const UART1_BASE_ADDR: usize = 0x40010000;

/// Peripheral size for uart1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #UART1_BASE_ADDR and
/// `UART1_BASE_ADDR + UART1_SIZE_BYTES`.
pub const UART1_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart2 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const UART2_BASE_ADDR: usize = 0x40020000;

/// Peripheral size for uart2 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #UART2_BASE_ADDR and
/// `UART2_BASE_ADDR + UART2_SIZE_BYTES`.
pub const UART2_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for uart3 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const UART3_BASE_ADDR: usize = 0x40030000;

/// Peripheral size for uart3 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #UART3_BASE_ADDR and
/// `UART3_BASE_ADDR + UART3_SIZE_BYTES`.
pub const UART3_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for gpio in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const GPIO_BASE_ADDR: usize = 0x40040000;

/// Peripheral size for gpio in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #GPIO_BASE_ADDR and
/// `GPIO_BASE_ADDR + GPIO_SIZE_BYTES`.
pub const GPIO_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for spi_device in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SPI_DEVICE_BASE_ADDR: usize = 0x40050000;

/// Peripheral size for spi_device in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SPI_DEVICE_BASE_ADDR and
/// `SPI_DEVICE_BASE_ADDR + SPI_DEVICE_SIZE_BYTES`.
pub const SPI_DEVICE_SIZE_BYTES: usize = 0x2000;

/// Peripheral base address for i2c0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const I2C0_BASE_ADDR: usize = 0x40080000;

/// Peripheral size for i2c0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #I2C0_BASE_ADDR and
/// `I2C0_BASE_ADDR + I2C0_SIZE_BYTES`.
pub const I2C0_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for i2c1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const I2C1_BASE_ADDR: usize = 0x40090000;

/// Peripheral size for i2c1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #I2C1_BASE_ADDR and
/// `I2C1_BASE_ADDR + I2C1_SIZE_BYTES`.
pub const I2C1_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for i2c2 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const I2C2_BASE_ADDR: usize = 0x400A0000;

/// Peripheral size for i2c2 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #I2C2_BASE_ADDR and
/// `I2C2_BASE_ADDR + I2C2_SIZE_BYTES`.
pub const I2C2_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pattgen in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const PATTGEN_BASE_ADDR: usize = 0x400E0000;

/// Peripheral size for pattgen in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #PATTGEN_BASE_ADDR and
/// `PATTGEN_BASE_ADDR + PATTGEN_SIZE_BYTES`.
pub const PATTGEN_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for rv_timer in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_TIMER_BASE_ADDR: usize = 0x40100000;

/// Peripheral size for rv_timer in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_TIMER_BASE_ADDR and
/// `RV_TIMER_BASE_ADDR + RV_TIMER_SIZE_BYTES`.
pub const RV_TIMER_SIZE_BYTES: usize = 0x200;

/// Peripheral base address for core device on otp_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const OTP_CTRL_CORE_BASE_ADDR: usize = 0x40130000;

/// Peripheral size for core device on otp_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #OTP_CTRL_CORE_BASE_ADDR and
/// `OTP_CTRL_CORE_BASE_ADDR + OTP_CTRL_CORE_SIZE_BYTES`.
pub const OTP_CTRL_CORE_SIZE_BYTES: usize = 0x2000;

/// Peripheral base address for prim device on otp_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const OTP_CTRL_PRIM_BASE_ADDR: usize = 0x40132000;

/// Peripheral size for prim device on otp_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #OTP_CTRL_PRIM_BASE_ADDR and
/// `OTP_CTRL_PRIM_BASE_ADDR + OTP_CTRL_PRIM_SIZE_BYTES`.
pub const OTP_CTRL_PRIM_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for lc_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const LC_CTRL_BASE_ADDR: usize = 0x40140000;

/// Peripheral size for lc_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #LC_CTRL_BASE_ADDR and
/// `LC_CTRL_BASE_ADDR + LC_CTRL_SIZE_BYTES`.
pub const LC_CTRL_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for alert_handler in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const ALERT_HANDLER_BASE_ADDR: usize = 0x40150000;

/// Peripheral size for alert_handler in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #ALERT_HANDLER_BASE_ADDR and
/// `ALERT_HANDLER_BASE_ADDR + ALERT_HANDLER_SIZE_BYTES`.
pub const ALERT_HANDLER_SIZE_BYTES: usize = 0x800;

/// Peripheral base address for spi_host0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SPI_HOST0_BASE_ADDR: usize = 0x40300000;

/// Peripheral size for spi_host0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SPI_HOST0_BASE_ADDR and
/// `SPI_HOST0_BASE_ADDR + SPI_HOST0_SIZE_BYTES`.
pub const SPI_HOST0_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for spi_host1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SPI_HOST1_BASE_ADDR: usize = 0x40310000;

/// Peripheral size for spi_host1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SPI_HOST1_BASE_ADDR and
/// `SPI_HOST1_BASE_ADDR + SPI_HOST1_SIZE_BYTES`.
pub const SPI_HOST1_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for usbdev in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const USBDEV_BASE_ADDR: usize = 0x40320000;

/// Peripheral size for usbdev in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #USBDEV_BASE_ADDR and
/// `USBDEV_BASE_ADDR + USBDEV_SIZE_BYTES`.
pub const USBDEV_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for pwrmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const PWRMGR_AON_BASE_ADDR: usize = 0x40400000;

/// Peripheral size for pwrmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #PWRMGR_AON_BASE_ADDR and
/// `PWRMGR_AON_BASE_ADDR + PWRMGR_AON_SIZE_BYTES`.
pub const PWRMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for rstmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RSTMGR_AON_BASE_ADDR: usize = 0x40410000;

/// Peripheral size for rstmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RSTMGR_AON_BASE_ADDR and
/// `RSTMGR_AON_BASE_ADDR + RSTMGR_AON_SIZE_BYTES`.
pub const RSTMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for clkmgr_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const CLKMGR_AON_BASE_ADDR: usize = 0x40420000;

/// Peripheral size for clkmgr_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #CLKMGR_AON_BASE_ADDR and
/// `CLKMGR_AON_BASE_ADDR + CLKMGR_AON_SIZE_BYTES`.
pub const CLKMGR_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for sysrst_ctrl_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SYSRST_CTRL_AON_BASE_ADDR: usize = 0x40430000;

/// Peripheral size for sysrst_ctrl_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SYSRST_CTRL_AON_BASE_ADDR and
/// `SYSRST_CTRL_AON_BASE_ADDR + SYSRST_CTRL_AON_SIZE_BYTES`.
pub const SYSRST_CTRL_AON_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for adc_ctrl_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const ADC_CTRL_AON_BASE_ADDR: usize = 0x40440000;

/// Peripheral size for adc_ctrl_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #ADC_CTRL_AON_BASE_ADDR and
/// `ADC_CTRL_AON_BASE_ADDR + ADC_CTRL_AON_SIZE_BYTES`.
pub const ADC_CTRL_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pwm_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const PWM_AON_BASE_ADDR: usize = 0x40450000;

/// Peripheral size for pwm_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #PWM_AON_BASE_ADDR and
/// `PWM_AON_BASE_ADDR + PWM_AON_SIZE_BYTES`.
pub const PWM_AON_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for pinmux_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const PINMUX_AON_BASE_ADDR: usize = 0x40460000;

/// Peripheral size for pinmux_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #PINMUX_AON_BASE_ADDR and
/// `PINMUX_AON_BASE_ADDR + PINMUX_AON_SIZE_BYTES`.
pub const PINMUX_AON_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for aon_timer_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const AON_TIMER_AON_BASE_ADDR: usize = 0x40470000;

/// Peripheral size for aon_timer_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #AON_TIMER_AON_BASE_ADDR and
/// `AON_TIMER_AON_BASE_ADDR + AON_TIMER_AON_SIZE_BYTES`.
pub const AON_TIMER_AON_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for ast in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const AST_BASE_ADDR: usize = 0x40480000;

/// Peripheral size for ast in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #AST_BASE_ADDR and
/// `AST_BASE_ADDR + AST_SIZE_BYTES`.
pub const AST_SIZE_BYTES: usize = 0x400;

/// Peripheral base address for sensor_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SENSOR_CTRL_BASE_ADDR: usize = 0x40490000;

/// Peripheral size for sensor_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SENSOR_CTRL_BASE_ADDR and
/// `SENSOR_CTRL_BASE_ADDR + SENSOR_CTRL_SIZE_BYTES`.
pub const SENSOR_CTRL_SIZE_BYTES: usize = 0x40;

/// Peripheral base address for regs device on sram_ctrl_ret_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SRAM_CTRL_RET_AON_REGS_BASE_ADDR: usize = 0x40500000;

/// Peripheral size for regs device on sram_ctrl_ret_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SRAM_CTRL_RET_AON_REGS_BASE_ADDR and
/// `SRAM_CTRL_RET_AON_REGS_BASE_ADDR + SRAM_CTRL_RET_AON_REGS_SIZE_BYTES`.
pub const SRAM_CTRL_RET_AON_REGS_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for ram device on sram_ctrl_ret_aon in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SRAM_CTRL_RET_AON_RAM_BASE_ADDR: usize = 0x40600000;

/// Peripheral size for ram device on sram_ctrl_ret_aon in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SRAM_CTRL_RET_AON_RAM_BASE_ADDR and
/// `SRAM_CTRL_RET_AON_RAM_BASE_ADDR + SRAM_CTRL_RET_AON_RAM_SIZE_BYTES`.
pub const SRAM_CTRL_RET_AON_RAM_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for core device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000;

/// Peripheral size for core device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #FLASH_CTRL_CORE_BASE_ADDR and
/// `FLASH_CTRL_CORE_BASE_ADDR + FLASH_CTRL_CORE_SIZE_BYTES`.
pub const FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200;

/// Peripheral base address for prim device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000;

/// Peripheral size for prim device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #FLASH_CTRL_PRIM_BASE_ADDR and
/// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`.
pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for mem device on flash_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const FLASH_CTRL_MEM_BASE_ADDR: usize = 0x20000000;

/// Peripheral size for mem device on flash_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #FLASH_CTRL_MEM_BASE_ADDR and
/// `FLASH_CTRL_MEM_BASE_ADDR + FLASH_CTRL_MEM_SIZE_BYTES`.
pub const FLASH_CTRL_MEM_SIZE_BYTES: usize = 0x100000;

/// Peripheral base address for regs device on rv_dm in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_DM_REGS_BASE_ADDR: usize = 0x41200000;

/// Peripheral size for regs device on rv_dm in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_DM_REGS_BASE_ADDR and
/// `RV_DM_REGS_BASE_ADDR + RV_DM_REGS_SIZE_BYTES`.
pub const RV_DM_REGS_SIZE_BYTES: usize = 0x4;

/// Peripheral base address for mem device on rv_dm in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_DM_MEM_BASE_ADDR: usize = 0x10000;

/// Peripheral size for mem device on rv_dm in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_DM_MEM_BASE_ADDR and
/// `RV_DM_MEM_BASE_ADDR + RV_DM_MEM_SIZE_BYTES`.
pub const RV_DM_MEM_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for rv_plic in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_PLIC_BASE_ADDR: usize = 0x48000000;

/// Peripheral size for rv_plic in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_PLIC_BASE_ADDR and
/// `RV_PLIC_BASE_ADDR + RV_PLIC_SIZE_BYTES`.
pub const RV_PLIC_SIZE_BYTES: usize = 0x8000000;

/// Peripheral base address for aes in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const AES_BASE_ADDR: usize = 0x41100000;

/// Peripheral size for aes in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #AES_BASE_ADDR and
/// `AES_BASE_ADDR + AES_SIZE_BYTES`.
pub const AES_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for hmac in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const HMAC_BASE_ADDR: usize = 0x41110000;

/// Peripheral size for hmac in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #HMAC_BASE_ADDR and
/// `HMAC_BASE_ADDR + HMAC_SIZE_BYTES`.
pub const HMAC_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for kmac in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const KMAC_BASE_ADDR: usize = 0x41120000;

/// Peripheral size for kmac in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #KMAC_BASE_ADDR and
/// `KMAC_BASE_ADDR + KMAC_SIZE_BYTES`.
pub const KMAC_SIZE_BYTES: usize = 0x1000;

/// Peripheral base address for otbn in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const OTBN_BASE_ADDR: usize = 0x41130000;

/// Peripheral size for otbn in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #OTBN_BASE_ADDR and
/// `OTBN_BASE_ADDR + OTBN_SIZE_BYTES`.
pub const OTBN_SIZE_BYTES: usize = 0x10000;

/// Peripheral base address for keymgr in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const KEYMGR_BASE_ADDR: usize = 0x41140000;

/// Peripheral size for keymgr in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #KEYMGR_BASE_ADDR and
/// `KEYMGR_BASE_ADDR + KEYMGR_SIZE_BYTES`.
pub const KEYMGR_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for csrng in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const CSRNG_BASE_ADDR: usize = 0x41150000;

/// Peripheral size for csrng in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #CSRNG_BASE_ADDR and
/// `CSRNG_BASE_ADDR + CSRNG_SIZE_BYTES`.
pub const CSRNG_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for entropy_src in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const ENTROPY_SRC_BASE_ADDR: usize = 0x41160000;

/// Peripheral size for entropy_src in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #ENTROPY_SRC_BASE_ADDR and
/// `ENTROPY_SRC_BASE_ADDR + ENTROPY_SRC_SIZE_BYTES`.
pub const ENTROPY_SRC_SIZE_BYTES: usize = 0x100;

/// Peripheral base address for edn0 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const EDN0_BASE_ADDR: usize = 0x41170000;

/// Peripheral size for edn0 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #EDN0_BASE_ADDR and
/// `EDN0_BASE_ADDR + EDN0_SIZE_BYTES`.
pub const EDN0_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for edn1 in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const EDN1_BASE_ADDR: usize = 0x41180000;

/// Peripheral size for edn1 in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #EDN1_BASE_ADDR and
/// `EDN1_BASE_ADDR + EDN1_SIZE_BYTES`.
pub const EDN1_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for regs device on sram_ctrl_main in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SRAM_CTRL_MAIN_REGS_BASE_ADDR: usize = 0x411C0000;

/// Peripheral size for regs device on sram_ctrl_main in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SRAM_CTRL_MAIN_REGS_BASE_ADDR and
/// `SRAM_CTRL_MAIN_REGS_BASE_ADDR + SRAM_CTRL_MAIN_REGS_SIZE_BYTES`.
pub const SRAM_CTRL_MAIN_REGS_SIZE_BYTES: usize = 0x20;

/// Peripheral base address for ram device on sram_ctrl_main in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const SRAM_CTRL_MAIN_RAM_BASE_ADDR: usize = 0x10000000;

/// Peripheral size for ram device on sram_ctrl_main in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #SRAM_CTRL_MAIN_RAM_BASE_ADDR and
/// `SRAM_CTRL_MAIN_RAM_BASE_ADDR + SRAM_CTRL_MAIN_RAM_SIZE_BYTES`.
pub const SRAM_CTRL_MAIN_RAM_SIZE_BYTES: usize = 0x20000;

/// Peripheral base address for regs device on rom_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const ROM_CTRL_REGS_BASE_ADDR: usize = 0x411E0000;

/// Peripheral size for regs device on rom_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #ROM_CTRL_REGS_BASE_ADDR and
/// `ROM_CTRL_REGS_BASE_ADDR + ROM_CTRL_REGS_SIZE_BYTES`.
pub const ROM_CTRL_REGS_SIZE_BYTES: usize = 0x80;

/// Peripheral base address for rom device on rom_ctrl in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const ROM_CTRL_ROM_BASE_ADDR: usize = 0x8000;

/// Peripheral size for rom device on rom_ctrl in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #ROM_CTRL_ROM_BASE_ADDR and
/// `ROM_CTRL_ROM_BASE_ADDR + ROM_CTRL_ROM_SIZE_BYTES`.
pub const ROM_CTRL_ROM_SIZE_BYTES: usize = 0x8000;

/// Peripheral base address for cfg device on rv_core_ibex in top earlgrey.
///
/// This should be used with #mmio_region_from_addr to access the memory-mapped
/// registers associated with the peripheral (usually via a DIF).
pub const RV_CORE_IBEX_CFG_BASE_ADDR: usize = 0x411F0000;

/// Peripheral size for cfg device on rv_core_ibex in top earlgrey.
///
/// This is the size (in bytes) of the peripheral's reserved memory area. All
/// memory-mapped registers associated with this peripheral should have an
/// address between #RV_CORE_IBEX_CFG_BASE_ADDR and
/// `RV_CORE_IBEX_CFG_BASE_ADDR + RV_CORE_IBEX_CFG_SIZE_BYTES`.
pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x100;

/// Memory base address for ram_ret_aon in top earlgrey.
pub const RAM_RET_AON_BASE_ADDR: usize = 0x40600000;

/// Memory size for ram_ret_aon in top earlgrey.
pub const RAM_RET_AON_SIZE_BYTES: usize = 0x1000;

/// Memory base address for eflash in top earlgrey.
pub const EFLASH_BASE_ADDR: usize = 0x20000000;

/// Memory size for eflash in top earlgrey.
pub const EFLASH_SIZE_BYTES: usize = 0x100000;

/// Memory base address for ram_main in top earlgrey.
pub const RAM_MAIN_BASE_ADDR: usize = 0x10000000;

/// Memory size for ram_main in top earlgrey.
pub const RAM_MAIN_SIZE_BYTES: usize = 0x20000;

/// Memory base address for rom in top earlgrey.
pub const ROM_BASE_ADDR: usize = 0x8000;

/// Memory size for rom in top earlgrey.
pub const ROM_SIZE_BYTES: usize = 0x8000;

/// PLIC Interrupt Source Peripheral.
///
/// Enumeration used to determine which peripheral asserted the corresponding
/// interrupt.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PlicPeripheral {
    /// Unknown Peripheral
    Unknown = 0,
    /// uart0
    Uart0 = 1,
    /// uart1
    Uart1 = 2,
    /// uart2
    Uart2 = 3,
    /// uart3
    Uart3 = 4,
    /// gpio
    Gpio = 5,
    /// spi_device
    SpiDevice = 6,
    /// i2c0
    I2c0 = 7,
    /// i2c1
    I2c1 = 8,
    /// i2c2
    I2c2 = 9,
    /// pattgen
    Pattgen = 10,
    /// rv_timer
    RvTimer = 11,
    /// otp_ctrl
    OtpCtrl = 12,
    /// alert_handler
    AlertHandler = 13,
    /// spi_host0
    SpiHost0 = 14,
    /// spi_host1
    SpiHost1 = 15,
    /// usbdev
    Usbdev = 16,
    /// pwrmgr_aon
    PwrmgrAon = 17,
    /// sysrst_ctrl_aon
    SysrstCtrlAon = 18,
    /// adc_ctrl_aon
    AdcCtrlAon = 19,
    /// aon_timer_aon
    AonTimerAon = 20,
    /// sensor_ctrl
    SensorCtrl = 21,
    /// flash_ctrl
    FlashCtrl = 22,
    /// hmac
    Hmac = 23,
    /// kmac
    Kmac = 24,
    /// otbn
    Otbn = 25,
    /// keymgr
    Keymgr = 26,
    /// csrng
    Csrng = 27,
    /// entropy_src
    EntropySrc = 28,
    /// edn0
    Edn0 = 29,
    /// edn1
    Edn1 = 30,
}

impl TryFrom<u32> for PlicPeripheral {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::Unknown),
            1 => Ok(Self::Uart0),
            2 => Ok(Self::Uart1),
            3 => Ok(Self::Uart2),
            4 => Ok(Self::Uart3),
            5 => Ok(Self::Gpio),
            6 => Ok(Self::SpiDevice),
            7 => Ok(Self::I2c0),
            8 => Ok(Self::I2c1),
            9 => Ok(Self::I2c2),
            10 => Ok(Self::Pattgen),
            11 => Ok(Self::RvTimer),
            12 => Ok(Self::OtpCtrl),
            13 => Ok(Self::AlertHandler),
            14 => Ok(Self::SpiHost0),
            15 => Ok(Self::SpiHost1),
            16 => Ok(Self::Usbdev),
            17 => Ok(Self::PwrmgrAon),
            18 => Ok(Self::SysrstCtrlAon),
            19 => Ok(Self::AdcCtrlAon),
            20 => Ok(Self::AonTimerAon),
            21 => Ok(Self::SensorCtrl),
            22 => Ok(Self::FlashCtrl),
            23 => Ok(Self::Hmac),
            24 => Ok(Self::Kmac),
            25 => Ok(Self::Otbn),
            26 => Ok(Self::Keymgr),
            27 => Ok(Self::Csrng),
            28 => Ok(Self::EntropySrc),
            29 => Ok(Self::Edn0),
            30 => Ok(Self::Edn1),
            _ => Err(val),
        }
    }
}

/// PLIC Interrupt Source.
///
/// Enumeration of all PLIC interrupt sources. The interrupt sources belonging to
/// the same peripheral are guaranteed to be consecutive.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PlicIrqId {
    /// No Interrupt
    None = 0,
    /// uart0_tx_watermark
    Uart0TxWatermark = 1,
    /// uart0_rx_watermark
    Uart0RxWatermark = 2,
    /// uart0_tx_empty
    Uart0TxEmpty = 3,
    /// uart0_rx_overflow
    Uart0RxOverflow = 4,
    /// uart0_rx_frame_err
    Uart0RxFrameErr = 5,
    /// uart0_rx_break_err
    Uart0RxBreakErr = 6,
    /// uart0_rx_timeout
    Uart0RxTimeout = 7,
    /// uart0_rx_parity_err
    Uart0RxParityErr = 8,
    /// uart1_tx_watermark
    Uart1TxWatermark = 9,
    /// uart1_rx_watermark
    Uart1RxWatermark = 10,
    /// uart1_tx_empty
    Uart1TxEmpty = 11,
    /// uart1_rx_overflow
    Uart1RxOverflow = 12,
    /// uart1_rx_frame_err
    Uart1RxFrameErr = 13,
    /// uart1_rx_break_err
    Uart1RxBreakErr = 14,
    /// uart1_rx_timeout
    Uart1RxTimeout = 15,
    /// uart1_rx_parity_err
    Uart1RxParityErr = 16,
    /// uart2_tx_watermark
    Uart2TxWatermark = 17,
    /// uart2_rx_watermark
    Uart2RxWatermark = 18,
    /// uart2_tx_empty
    Uart2TxEmpty = 19,
    /// uart2_rx_overflow
    Uart2RxOverflow = 20,
    /// uart2_rx_frame_err
    Uart2RxFrameErr = 21,
    /// uart2_rx_break_err
    Uart2RxBreakErr = 22,
    /// uart2_rx_timeout
    Uart2RxTimeout = 23,
    /// uart2_rx_parity_err
    Uart2RxParityErr = 24,
    /// uart3_tx_watermark
    Uart3TxWatermark = 25,
    /// uart3_rx_watermark
    Uart3RxWatermark = 26,
    /// uart3_tx_empty
    Uart3TxEmpty = 27,
    /// uart3_rx_overflow
    Uart3RxOverflow = 28,
    /// uart3_rx_frame_err
    Uart3RxFrameErr = 29,
    /// uart3_rx_break_err
    Uart3RxBreakErr = 30,
    /// uart3_rx_timeout
    Uart3RxTimeout = 31,
    /// uart3_rx_parity_err
    Uart3RxParityErr = 32,
    /// gpio_gpio 0
    GpioGpio0 = 33,
    /// gpio_gpio 1
    GpioGpio1 = 34,
    /// gpio_gpio 2
    GpioGpio2 = 35,
    /// gpio_gpio 3
    GpioGpio3 = 36,
    /// gpio_gpio 4
    GpioGpio4 = 37,
    /// gpio_gpio 5
    GpioGpio5 = 38,
    /// gpio_gpio 6
    GpioGpio6 = 39,
    /// gpio_gpio 7
    GpioGpio7 = 40,
    /// gpio_gpio 8
    GpioGpio8 = 41,
    /// gpio_gpio 9
    GpioGpio9 = 42,
    /// gpio_gpio 10
    GpioGpio10 = 43,
    /// gpio_gpio 11
    GpioGpio11 = 44,
    /// gpio_gpio 12
    GpioGpio12 = 45,
    /// gpio_gpio 13
    GpioGpio13 = 46,
    /// gpio_gpio 14
    GpioGpio14 = 47,
    /// gpio_gpio 15
    GpioGpio15 = 48,
    /// gpio_gpio 16
    GpioGpio16 = 49,
    /// gpio_gpio 17
    GpioGpio17 = 50,
    /// gpio_gpio 18
    GpioGpio18 = 51,
    /// gpio_gpio 19
    GpioGpio19 = 52,
    /// gpio_gpio 20
    GpioGpio20 = 53,
    /// gpio_gpio 21
    GpioGpio21 = 54,
    /// gpio_gpio 22
    GpioGpio22 = 55,
    /// gpio_gpio 23
    GpioGpio23 = 56,
    /// gpio_gpio 24
    GpioGpio24 = 57,
    /// gpio_gpio 25
    GpioGpio25 = 58,
    /// gpio_gpio 26
    GpioGpio26 = 59,
    /// gpio_gpio 27
    GpioGpio27 = 60,
    /// gpio_gpio 28
    GpioGpio28 = 61,
    /// gpio_gpio 29
    GpioGpio29 = 62,
    /// gpio_gpio 30
    GpioGpio30 = 63,
    /// gpio_gpio 31
    GpioGpio31 = 64,
    /// spi_device_generic_rx_full
    SpiDeviceGenericRxFull = 65,
    /// spi_device_generic_rx_watermark
    SpiDeviceGenericRxWatermark = 66,
    /// spi_device_generic_tx_watermark
    SpiDeviceGenericTxWatermark = 67,
    /// spi_device_generic_rx_error
    SpiDeviceGenericRxError = 68,
    /// spi_device_generic_rx_overflow
    SpiDeviceGenericRxOverflow = 69,
    /// spi_device_generic_tx_underflow
    SpiDeviceGenericTxUnderflow = 70,
    /// spi_device_upload_cmdfifo_not_empty
    SpiDeviceUploadCmdfifoNotEmpty = 71,
    /// spi_device_upload_payload_not_empty
    SpiDeviceUploadPayloadNotEmpty = 72,
    /// spi_device_upload_payload_overflow
    SpiDeviceUploadPayloadOverflow = 73,
    /// spi_device_readbuf_watermark
    SpiDeviceReadbufWatermark = 74,
    /// spi_device_readbuf_flip
    SpiDeviceReadbufFlip = 75,
    /// spi_device_tpm_header_not_empty
    SpiDeviceTpmHeaderNotEmpty = 76,
    /// i2c0_fmt_threshold
    I2c0FmtThreshold = 77,
    /// i2c0_rx_threshold
    I2c0RxThreshold = 78,
    /// i2c0_fmt_overflow
    I2c0FmtOverflow = 79,
    /// i2c0_rx_overflow
    I2c0RxOverflow = 80,
    /// i2c0_nak
    I2c0Nak = 81,
    /// i2c0_scl_interference
    I2c0SclInterference = 82,
    /// i2c0_sda_interference
    I2c0SdaInterference = 83,
    /// i2c0_stretch_timeout
    I2c0StretchTimeout = 84,
    /// i2c0_sda_unstable
    I2c0SdaUnstable = 85,
    /// i2c0_cmd_complete
    I2c0CmdComplete = 86,
    /// i2c0_tx_stretch
    I2c0TxStretch = 87,
    /// i2c0_tx_overflow
    I2c0TxOverflow = 88,
    /// i2c0_acq_full
    I2c0AcqFull = 89,
    /// i2c0_unexp_stop
    I2c0UnexpStop = 90,
    /// i2c0_host_timeout
    I2c0HostTimeout = 91,
    /// i2c1_fmt_threshold
    I2c1FmtThreshold = 92,
    /// i2c1_rx_threshold
    I2c1RxThreshold = 93,
    /// i2c1_fmt_overflow
    I2c1FmtOverflow = 94,
    /// i2c1_rx_overflow
    I2c1RxOverflow = 95,
    /// i2c1_nak
    I2c1Nak = 96,
    /// i2c1_scl_interference
    I2c1SclInterference = 97,
    /// i2c1_sda_interference
    I2c1SdaInterference = 98,
    /// i2c1_stretch_timeout
    I2c1StretchTimeout = 99,
    /// i2c1_sda_unstable
    I2c1SdaUnstable = 100,
    /// i2c1_cmd_complete
    I2c1CmdComplete = 101,
    /// i2c1_tx_stretch
    I2c1TxStretch = 102,
    /// i2c1_tx_overflow
    I2c1TxOverflow = 103,
    /// i2c1_acq_full
    I2c1AcqFull = 104,
    /// i2c1_unexp_stop
    I2c1UnexpStop = 105,
    /// i2c1_host_timeout
    I2c1HostTimeout = 106,
    /// i2c2_fmt_threshold
    I2c2FmtThreshold = 107,
    /// i2c2_rx_threshold
    I2c2RxThreshold = 108,
    /// i2c2_fmt_overflow
    I2c2FmtOverflow = 109,
    /// i2c2_rx_overflow
    I2c2RxOverflow = 110,
    /// i2c2_nak
    I2c2Nak = 111,
    /// i2c2_scl_interference
    I2c2SclInterference = 112,
    /// i2c2_sda_interference
    I2c2SdaInterference = 113,
    /// i2c2_stretch_timeout
    I2c2StretchTimeout = 114,
    /// i2c2_sda_unstable
    I2c2SdaUnstable = 115,
    /// i2c2_cmd_complete
    I2c2CmdComplete = 116,
    /// i2c2_tx_stretch
    I2c2TxStretch = 117,
    /// i2c2_tx_overflow
    I2c2TxOverflow = 118,
    /// i2c2_acq_full
    I2c2AcqFull = 119,
    /// i2c2_unexp_stop
    I2c2UnexpStop = 120,
    /// i2c2_host_timeout
    I2c2HostTimeout = 121,
    /// pattgen_done_ch0
    PattgenDoneCh0 = 122,
    /// pattgen_done_ch1
    PattgenDoneCh1 = 123,
    /// rv_timer_timer_expired_hart0_timer0
    RvTimerTimerExpiredHart0Timer0 = 124,
    /// otp_ctrl_otp_operation_done
    OtpCtrlOtpOperationDone = 125,
    /// otp_ctrl_otp_error
    OtpCtrlOtpError = 126,
    /// alert_handler_classa
    AlertHandlerClassa = 127,
    /// alert_handler_classb
    AlertHandlerClassb = 128,
    /// alert_handler_classc
    AlertHandlerClassc = 129,
    /// alert_handler_classd
    AlertHandlerClassd = 130,
    /// spi_host0_error
    SpiHost0Error = 131,
    /// spi_host0_spi_event
    SpiHost0SpiEvent = 132,
    /// spi_host1_error
    SpiHost1Error = 133,
    /// spi_host1_spi_event
    SpiHost1SpiEvent = 134,
    /// usbdev_pkt_received
    UsbdevPktReceived = 135,
    /// usbdev_pkt_sent
    UsbdevPktSent = 136,
    /// usbdev_disconnected
    UsbdevDisconnected = 137,
    /// usbdev_host_lost
    UsbdevHostLost = 138,
    /// usbdev_link_reset
    UsbdevLinkReset = 139,
    /// usbdev_link_suspend
    UsbdevLinkSuspend = 140,
    /// usbdev_link_resume
    UsbdevLinkResume = 141,
    /// usbdev_av_empty
    UsbdevAvEmpty = 142,
    /// usbdev_rx_full
    UsbdevRxFull = 143,
    /// usbdev_av_overflow
    UsbdevAvOverflow = 144,
    /// usbdev_link_in_err
    UsbdevLinkInErr = 145,
    /// usbdev_rx_crc_err
    UsbdevRxCrcErr = 146,
    /// usbdev_rx_pid_err
    UsbdevRxPidErr = 147,
    /// usbdev_rx_bitstuff_err
    UsbdevRxBitstuffErr = 148,
    /// usbdev_frame
    UsbdevFrame = 149,
    /// usbdev_powered
    UsbdevPowered = 150,
    /// usbdev_link_out_err
    UsbdevLinkOutErr = 151,
    /// pwrmgr_aon_wakeup
    PwrmgrAonWakeup = 152,
    /// sysrst_ctrl_aon_event_detected
    SysrstCtrlAonEventDetected = 153,
    /// adc_ctrl_aon_match_done
    AdcCtrlAonMatchDone = 154,
    /// aon_timer_aon_wkup_timer_expired
    AonTimerAonWkupTimerExpired = 155,
    /// aon_timer_aon_wdog_timer_bark
    AonTimerAonWdogTimerBark = 156,
    /// sensor_ctrl_io_status_change
    SensorCtrlIoStatusChange = 157,
    /// sensor_ctrl_init_status_change
    SensorCtrlInitStatusChange = 158,
    /// flash_ctrl_prog_empty
    FlashCtrlProgEmpty = 159,
    /// flash_ctrl_prog_lvl
    FlashCtrlProgLvl = 160,
    /// flash_ctrl_rd_full
    FlashCtrlRdFull = 161,
    /// flash_ctrl_rd_lvl
    FlashCtrlRdLvl = 162,
    /// flash_ctrl_op_done
    FlashCtrlOpDone = 163,
    /// flash_ctrl_corr_err
    FlashCtrlCorrErr = 164,
    /// hmac_hmac_done
    HmacHmacDone = 165,
    /// hmac_fifo_empty
    HmacFifoEmpty = 166,
    /// hmac_hmac_err
    HmacHmacErr = 167,
    /// kmac_kmac_done
    KmacKmacDone = 168,
    /// kmac_fifo_empty
    KmacFifoEmpty = 169,
    /// kmac_kmac_err
    KmacKmacErr = 170,
    /// otbn_done
    OtbnDone = 171,
    /// keymgr_op_done
    KeymgrOpDone = 172,
    /// csrng_cs_cmd_req_done
    CsrngCsCmdReqDone = 173,
    /// csrng_cs_entropy_req
    CsrngCsEntropyReq = 174,
    /// csrng_cs_hw_inst_exc
    CsrngCsHwInstExc = 175,
    /// csrng_cs_fatal_err
    CsrngCsFatalErr = 176,
    /// entropy_src_es_entropy_valid
    EntropySrcEsEntropyValid = 177,
    /// entropy_src_es_health_test_failed
    EntropySrcEsHealthTestFailed = 178,
    /// entropy_src_es_observe_fifo_ready
    EntropySrcEsObserveFifoReady = 179,
    /// entropy_src_es_fatal_err
    EntropySrcEsFatalErr = 180,
    /// edn0_edn_cmd_req_done
    Edn0EdnCmdReqDone = 181,
    /// edn0_edn_fatal_err
    Edn0EdnFatalErr = 182,
    /// edn1_edn_cmd_req_done
    Edn1EdnCmdReqDone = 183,
    /// edn1_edn_fatal_err
    Edn1EdnFatalErr = 184,
}

impl TryFrom<u32> for PlicIrqId {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::None),
            1 => Ok(Self::Uart0TxWatermark),
            2 => Ok(Self::Uart0RxWatermark),
            3 => Ok(Self::Uart0TxEmpty),
            4 => Ok(Self::Uart0RxOverflow),
            5 => Ok(Self::Uart0RxFrameErr),
            6 => Ok(Self::Uart0RxBreakErr),
            7 => Ok(Self::Uart0RxTimeout),
            8 => Ok(Self::Uart0RxParityErr),
            9 => Ok(Self::Uart1TxWatermark),
            10 => Ok(Self::Uart1RxWatermark),
            11 => Ok(Self::Uart1TxEmpty),
            12 => Ok(Self::Uart1RxOverflow),
            13 => Ok(Self::Uart1RxFrameErr),
            14 => Ok(Self::Uart1RxBreakErr),
            15 => Ok(Self::Uart1RxTimeout),
            16 => Ok(Self::Uart1RxParityErr),
            17 => Ok(Self::Uart2TxWatermark),
            18 => Ok(Self::Uart2RxWatermark),
            19 => Ok(Self::Uart2TxEmpty),
            20 => Ok(Self::Uart2RxOverflow),
            21 => Ok(Self::Uart2RxFrameErr),
            22 => Ok(Self::Uart2RxBreakErr),
            23 => Ok(Self::Uart2RxTimeout),
            24 => Ok(Self::Uart2RxParityErr),
            25 => Ok(Self::Uart3TxWatermark),
            26 => Ok(Self::Uart3RxWatermark),
            27 => Ok(Self::Uart3TxEmpty),
            28 => Ok(Self::Uart3RxOverflow),
            29 => Ok(Self::Uart3RxFrameErr),
            30 => Ok(Self::Uart3RxBreakErr),
            31 => Ok(Self::Uart3RxTimeout),
            32 => Ok(Self::Uart3RxParityErr),
            33 => Ok(Self::GpioGpio0),
            34 => Ok(Self::GpioGpio1),
            35 => Ok(Self::GpioGpio2),
            36 => Ok(Self::GpioGpio3),
            37 => Ok(Self::GpioGpio4),
            38 => Ok(Self::GpioGpio5),
            39 => Ok(Self::GpioGpio6),
            40 => Ok(Self::GpioGpio7),
            41 => Ok(Self::GpioGpio8),
            42 => Ok(Self::GpioGpio9),
            43 => Ok(Self::GpioGpio10),
            44 => Ok(Self::GpioGpio11),
            45 => Ok(Self::GpioGpio12),
            46 => Ok(Self::GpioGpio13),
            47 => Ok(Self::GpioGpio14),
            48 => Ok(Self::GpioGpio15),
            49 => Ok(Self::GpioGpio16),
            50 => Ok(Self::GpioGpio17),
            51 => Ok(Self::GpioGpio18),
            52 => Ok(Self::GpioGpio19),
            53 => Ok(Self::GpioGpio20),
            54 => Ok(Self::GpioGpio21),
            55 => Ok(Self::GpioGpio22),
            56 => Ok(Self::GpioGpio23),
            57 => Ok(Self::GpioGpio24),
            58 => Ok(Self::GpioGpio25),
            59 => Ok(Self::GpioGpio26),
            60 => Ok(Self::GpioGpio27),
            61 => Ok(Self::GpioGpio28),
            62 => Ok(Self::GpioGpio29),
            63 => Ok(Self::GpioGpio30),
            64 => Ok(Self::GpioGpio31),
            65 => Ok(Self::SpiDeviceGenericRxFull),
            66 => Ok(Self::SpiDeviceGenericRxWatermark),
            67 => Ok(Self::SpiDeviceGenericTxWatermark),
            68 => Ok(Self::SpiDeviceGenericRxError),
            69 => Ok(Self::SpiDeviceGenericRxOverflow),
            70 => Ok(Self::SpiDeviceGenericTxUnderflow),
            71 => Ok(Self::SpiDeviceUploadCmdfifoNotEmpty),
            72 => Ok(Self::SpiDeviceUploadPayloadNotEmpty),
            73 => Ok(Self::SpiDeviceUploadPayloadOverflow),
            74 => Ok(Self::SpiDeviceReadbufWatermark),
            75 => Ok(Self::SpiDeviceReadbufFlip),
            76 => Ok(Self::SpiDeviceTpmHeaderNotEmpty),
            77 => Ok(Self::I2c0FmtThreshold),
            78 => Ok(Self::I2c0RxThreshold),
            79 => Ok(Self::I2c0FmtOverflow),
            80 => Ok(Self::I2c0RxOverflow),
            81 => Ok(Self::I2c0Nak),
            82 => Ok(Self::I2c0SclInterference),
            83 => Ok(Self::I2c0SdaInterference),
            84 => Ok(Self::I2c0StretchTimeout),
            85 => Ok(Self::I2c0SdaUnstable),
            86 => Ok(Self::I2c0CmdComplete),
            87 => Ok(Self::I2c0TxStretch),
            88 => Ok(Self::I2c0TxOverflow),
            89 => Ok(Self::I2c0AcqFull),
            90 => Ok(Self::I2c0UnexpStop),
            91 => Ok(Self::I2c0HostTimeout),
            92 => Ok(Self::I2c1FmtThreshold),
            93 => Ok(Self::I2c1RxThreshold),
            94 => Ok(Self::I2c1FmtOverflow),
            95 => Ok(Self::I2c1RxOverflow),
            96 => Ok(Self::I2c1Nak),
            97 => Ok(Self::I2c1SclInterference),
            98 => Ok(Self::I2c1SdaInterference),
            99 => Ok(Self::I2c1StretchTimeout),
            100 => Ok(Self::I2c1SdaUnstable),
            101 => Ok(Self::I2c1CmdComplete),
            102 => Ok(Self::I2c1TxStretch),
            103 => Ok(Self::I2c1TxOverflow),
            104 => Ok(Self::I2c1AcqFull),
            105 => Ok(Self::I2c1UnexpStop),
            106 => Ok(Self::I2c1HostTimeout),
            107 => Ok(Self::I2c2FmtThreshold),
            108 => Ok(Self::I2c2RxThreshold),
            109 => Ok(Self::I2c2FmtOverflow),
            110 => Ok(Self::I2c2RxOverflow),
            111 => Ok(Self::I2c2Nak),
            112 => Ok(Self::I2c2SclInterference),
            113 => Ok(Self::I2c2SdaInterference),
            114 => Ok(Self::I2c2StretchTimeout),
            115 => Ok(Self::I2c2SdaUnstable),
            116 => Ok(Self::I2c2CmdComplete),
            117 => Ok(Self::I2c2TxStretch),
            118 => Ok(Self::I2c2TxOverflow),
            119 => Ok(Self::I2c2AcqFull),
            120 => Ok(Self::I2c2UnexpStop),
            121 => Ok(Self::I2c2HostTimeout),
            122 => Ok(Self::PattgenDoneCh0),
            123 => Ok(Self::PattgenDoneCh1),
            124 => Ok(Self::RvTimerTimerExpiredHart0Timer0),
            125 => Ok(Self::OtpCtrlOtpOperationDone),
            126 => Ok(Self::OtpCtrlOtpError),
            127 => Ok(Self::AlertHandlerClassa),
            128 => Ok(Self::AlertHandlerClassb),
            129 => Ok(Self::AlertHandlerClassc),
            130 => Ok(Self::AlertHandlerClassd),
            131 => Ok(Self::SpiHost0Error),
            132 => Ok(Self::SpiHost0SpiEvent),
            133 => Ok(Self::SpiHost1Error),
            134 => Ok(Self::SpiHost1SpiEvent),
            135 => Ok(Self::UsbdevPktReceived),
            136 => Ok(Self::UsbdevPktSent),
            137 => Ok(Self::UsbdevDisconnected),
            138 => Ok(Self::UsbdevHostLost),
            139 => Ok(Self::UsbdevLinkReset),
            140 => Ok(Self::UsbdevLinkSuspend),
            141 => Ok(Self::UsbdevLinkResume),
            142 => Ok(Self::UsbdevAvEmpty),
            143 => Ok(Self::UsbdevRxFull),
            144 => Ok(Self::UsbdevAvOverflow),
            145 => Ok(Self::UsbdevLinkInErr),
            146 => Ok(Self::UsbdevRxCrcErr),
            147 => Ok(Self::UsbdevRxPidErr),
            148 => Ok(Self::UsbdevRxBitstuffErr),
            149 => Ok(Self::UsbdevFrame),
            150 => Ok(Self::UsbdevPowered),
            151 => Ok(Self::UsbdevLinkOutErr),
            152 => Ok(Self::PwrmgrAonWakeup),
            153 => Ok(Self::SysrstCtrlAonEventDetected),
            154 => Ok(Self::AdcCtrlAonMatchDone),
            155 => Ok(Self::AonTimerAonWkupTimerExpired),
            156 => Ok(Self::AonTimerAonWdogTimerBark),
            157 => Ok(Self::SensorCtrlIoStatusChange),
            158 => Ok(Self::SensorCtrlInitStatusChange),
            159 => Ok(Self::FlashCtrlProgEmpty),
            160 => Ok(Self::FlashCtrlProgLvl),
            161 => Ok(Self::FlashCtrlRdFull),
            162 => Ok(Self::FlashCtrlRdLvl),
            163 => Ok(Self::FlashCtrlOpDone),
            164 => Ok(Self::FlashCtrlCorrErr),
            165 => Ok(Self::HmacHmacDone),
            166 => Ok(Self::HmacFifoEmpty),
            167 => Ok(Self::HmacHmacErr),
            168 => Ok(Self::KmacKmacDone),
            169 => Ok(Self::KmacFifoEmpty),
            170 => Ok(Self::KmacKmacErr),
            171 => Ok(Self::OtbnDone),
            172 => Ok(Self::KeymgrOpDone),
            173 => Ok(Self::CsrngCsCmdReqDone),
            174 => Ok(Self::CsrngCsEntropyReq),
            175 => Ok(Self::CsrngCsHwInstExc),
            176 => Ok(Self::CsrngCsFatalErr),
            177 => Ok(Self::EntropySrcEsEntropyValid),
            178 => Ok(Self::EntropySrcEsHealthTestFailed),
            179 => Ok(Self::EntropySrcEsObserveFifoReady),
            180 => Ok(Self::EntropySrcEsFatalErr),
            181 => Ok(Self::Edn0EdnCmdReqDone),
            182 => Ok(Self::Edn0EdnFatalErr),
            183 => Ok(Self::Edn1EdnCmdReqDone),
            184 => Ok(Self::Edn1EdnFatalErr),
            _ => Err(val),
        }
    }
}

/// PLIC Interrupt Target.
///
/// Enumeration used to determine which set of IE, CC, threshold registers to
/// access for a given interrupt target.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PlicTarget {
    /// Ibex Core 0
    Ibex0 = 0,
}

/// Alert Handler Source Peripheral.
///
/// Enumeration used to determine which peripheral asserted the corresponding
/// alert.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum AlertPeripheral {
    /// uart0
    Uart0 = 0,
    /// uart1
    Uart1 = 1,
    /// uart2
    Uart2 = 2,
    /// uart3
    Uart3 = 3,
    /// gpio
    Gpio = 4,
    /// spi_device
    SpiDevice = 5,
    /// i2c0
    I2c0 = 6,
    /// i2c1
    I2c1 = 7,
    /// i2c2
    I2c2 = 8,
    /// pattgen
    Pattgen = 9,
    /// rv_timer
    RvTimer = 10,
    /// otp_ctrl
    OtpCtrl = 11,
    /// lc_ctrl
    LcCtrl = 12,
    /// spi_host0
    SpiHost0 = 13,
    /// spi_host1
    SpiHost1 = 14,
    /// usbdev
    Usbdev = 15,
    /// pwrmgr_aon
    PwrmgrAon = 16,
    /// rstmgr_aon
    RstmgrAon = 17,
    /// clkmgr_aon
    ClkmgrAon = 18,
    /// sysrst_ctrl_aon
    SysrstCtrlAon = 19,
    /// adc_ctrl_aon
    AdcCtrlAon = 20,
    /// pwm_aon
    PwmAon = 21,
    /// pinmux_aon
    PinmuxAon = 22,
    /// aon_timer_aon
    AonTimerAon = 23,
    /// sensor_ctrl
    SensorCtrl = 24,
    /// sram_ctrl_ret_aon
    SramCtrlRetAon = 25,
    /// flash_ctrl
    FlashCtrl = 26,
    /// rv_dm
    RvDm = 27,
    /// rv_plic
    RvPlic = 28,
    /// aes
    Aes = 29,
    /// hmac
    Hmac = 30,
    /// kmac
    Kmac = 31,
    /// otbn
    Otbn = 32,
    /// keymgr
    Keymgr = 33,
    /// csrng
    Csrng = 34,
    /// entropy_src
    EntropySrc = 35,
    /// edn0
    Edn0 = 36,
    /// edn1
    Edn1 = 37,
    /// sram_ctrl_main
    SramCtrlMain = 38,
    /// rom_ctrl
    RomCtrl = 39,
    /// rv_core_ibex
    RvCoreIbex = 40,
}

/// Alert Handler Alert Source.
///
/// Enumeration of all Alert Handler Alert Sources. The alert sources belonging to
/// the same peripheral are guaranteed to be consecutive.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum AlertId {
    /// uart0_fatal_fault
    Uart0FatalFault = 0,
    /// uart1_fatal_fault
    Uart1FatalFault = 1,
    /// uart2_fatal_fault
    Uart2FatalFault = 2,
    /// uart3_fatal_fault
    Uart3FatalFault = 3,
    /// gpio_fatal_fault
    GpioFatalFault = 4,
    /// spi_device_fatal_fault
    SpiDeviceFatalFault = 5,
    /// i2c0_fatal_fault
    I2c0FatalFault = 6,
    /// i2c1_fatal_fault
    I2c1FatalFault = 7,
    /// i2c2_fatal_fault
    I2c2FatalFault = 8,
    /// pattgen_fatal_fault
    PattgenFatalFault = 9,
    /// rv_timer_fatal_fault
    RvTimerFatalFault = 10,
    /// otp_ctrl_fatal_macro_error
    OtpCtrlFatalMacroError = 11,
    /// otp_ctrl_fatal_check_error
    OtpCtrlFatalCheckError = 12,
    /// otp_ctrl_fatal_bus_integ_error
    OtpCtrlFatalBusIntegError = 13,
    /// otp_ctrl_fatal_prim_otp_alert
    OtpCtrlFatalPrimOtpAlert = 14,
    /// otp_ctrl_recov_prim_otp_alert
    OtpCtrlRecovPrimOtpAlert = 15,
    /// lc_ctrl_fatal_prog_error
    LcCtrlFatalProgError = 16,
    /// lc_ctrl_fatal_state_error
    LcCtrlFatalStateError = 17,
    /// lc_ctrl_fatal_bus_integ_error
    LcCtrlFatalBusIntegError = 18,
    /// spi_host0_fatal_fault
    SpiHost0FatalFault = 19,
    /// spi_host1_fatal_fault
    SpiHost1FatalFault = 20,
    /// usbdev_fatal_fault
    UsbdevFatalFault = 21,
    /// pwrmgr_aon_fatal_fault
    PwrmgrAonFatalFault = 22,
    /// rstmgr_aon_fatal_fault
    RstmgrAonFatalFault = 23,
    /// rstmgr_aon_fatal_cnsty_fault
    RstmgrAonFatalCnstyFault = 24,
    /// clkmgr_aon_recov_fault
    ClkmgrAonRecovFault = 25,
    /// clkmgr_aon_fatal_fault
    ClkmgrAonFatalFault = 26,
    /// sysrst_ctrl_aon_fatal_fault
    SysrstCtrlAonFatalFault = 27,
    /// adc_ctrl_aon_fatal_fault
    AdcCtrlAonFatalFault = 28,
    /// pwm_aon_fatal_fault
    PwmAonFatalFault = 29,
    /// pinmux_aon_fatal_fault
    PinmuxAonFatalFault = 30,
    /// aon_timer_aon_fatal_fault
    AonTimerAonFatalFault = 31,
    /// sensor_ctrl_recov_alert
    SensorCtrlRecovAlert = 32,
    /// sensor_ctrl_fatal_alert
    SensorCtrlFatalAlert = 33,
    /// sram_ctrl_ret_aon_fatal_error
    SramCtrlRetAonFatalError = 34,
    /// flash_ctrl_recov_err
    FlashCtrlRecovErr = 35,
    /// flash_ctrl_fatal_std_err
    FlashCtrlFatalStdErr = 36,
    /// flash_ctrl_fatal_err
    FlashCtrlFatalErr = 37,
    /// flash_ctrl_fatal_prim_flash_alert
    FlashCtrlFatalPrimFlashAlert = 38,
    /// flash_ctrl_recov_prim_flash_alert
    FlashCtrlRecovPrimFlashAlert = 39,
    /// rv_dm_fatal_fault
    RvDmFatalFault = 40,
    /// rv_plic_fatal_fault
    RvPlicFatalFault = 41,
    /// aes_recov_ctrl_update_err
    AesRecovCtrlUpdateErr = 42,
    /// aes_fatal_fault
    AesFatalFault = 43,
    /// hmac_fatal_fault
    HmacFatalFault = 44,
    /// kmac_recov_operation_err
    KmacRecovOperationErr = 45,
    /// kmac_fatal_fault_err
    KmacFatalFaultErr = 46,
    /// otbn_fatal
    OtbnFatal = 47,
    /// otbn_recov
    OtbnRecov = 48,
    /// keymgr_recov_operation_err
    KeymgrRecovOperationErr = 49,
    /// keymgr_fatal_fault_err
    KeymgrFatalFaultErr = 50,
    /// csrng_recov_alert
    CsrngRecovAlert = 51,
    /// csrng_fatal_alert
    CsrngFatalAlert = 52,
    /// entropy_src_recov_alert
    EntropySrcRecovAlert = 53,
    /// entropy_src_fatal_alert
    EntropySrcFatalAlert = 54,
    /// edn0_recov_alert
    Edn0RecovAlert = 55,
    /// edn0_fatal_alert
    Edn0FatalAlert = 56,
    /// edn1_recov_alert
    Edn1RecovAlert = 57,
    /// edn1_fatal_alert
    Edn1FatalAlert = 58,
    /// sram_ctrl_main_fatal_error
    SramCtrlMainFatalError = 59,
    /// rom_ctrl_fatal
    RomCtrlFatal = 60,
    /// rv_core_ibex_fatal_sw_err
    RvCoreIbexFatalSwErr = 61,
    /// rv_core_ibex_recov_sw_err
    RvCoreIbexRecovSwErr = 62,
    /// rv_core_ibex_fatal_hw_err
    RvCoreIbexFatalHwErr = 63,
    /// rv_core_ibex_recov_hw_err
    RvCoreIbexRecovHwErr = 64,
}

impl TryFrom<u32> for AlertId {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::Uart0FatalFault),
            1 => Ok(Self::Uart1FatalFault),
            2 => Ok(Self::Uart2FatalFault),
            3 => Ok(Self::Uart3FatalFault),
            4 => Ok(Self::GpioFatalFault),
            5 => Ok(Self::SpiDeviceFatalFault),
            6 => Ok(Self::I2c0FatalFault),
            7 => Ok(Self::I2c1FatalFault),
            8 => Ok(Self::I2c2FatalFault),
            9 => Ok(Self::PattgenFatalFault),
            10 => Ok(Self::RvTimerFatalFault),
            11 => Ok(Self::OtpCtrlFatalMacroError),
            12 => Ok(Self::OtpCtrlFatalCheckError),
            13 => Ok(Self::OtpCtrlFatalBusIntegError),
            14 => Ok(Self::OtpCtrlFatalPrimOtpAlert),
            15 => Ok(Self::OtpCtrlRecovPrimOtpAlert),
            16 => Ok(Self::LcCtrlFatalProgError),
            17 => Ok(Self::LcCtrlFatalStateError),
            18 => Ok(Self::LcCtrlFatalBusIntegError),
            19 => Ok(Self::SpiHost0FatalFault),
            20 => Ok(Self::SpiHost1FatalFault),
            21 => Ok(Self::UsbdevFatalFault),
            22 => Ok(Self::PwrmgrAonFatalFault),
            23 => Ok(Self::RstmgrAonFatalFault),
            24 => Ok(Self::RstmgrAonFatalCnstyFault),
            25 => Ok(Self::ClkmgrAonRecovFault),
            26 => Ok(Self::ClkmgrAonFatalFault),
            27 => Ok(Self::SysrstCtrlAonFatalFault),
            28 => Ok(Self::AdcCtrlAonFatalFault),
            29 => Ok(Self::PwmAonFatalFault),
            30 => Ok(Self::PinmuxAonFatalFault),
            31 => Ok(Self::AonTimerAonFatalFault),
            32 => Ok(Self::SensorCtrlRecovAlert),
            33 => Ok(Self::SensorCtrlFatalAlert),
            34 => Ok(Self::SramCtrlRetAonFatalError),
            35 => Ok(Self::FlashCtrlRecovErr),
            36 => Ok(Self::FlashCtrlFatalStdErr),
            37 => Ok(Self::FlashCtrlFatalErr),
            38 => Ok(Self::FlashCtrlFatalPrimFlashAlert),
            39 => Ok(Self::FlashCtrlRecovPrimFlashAlert),
            40 => Ok(Self::RvDmFatalFault),
            41 => Ok(Self::RvPlicFatalFault),
            42 => Ok(Self::AesRecovCtrlUpdateErr),
            43 => Ok(Self::AesFatalFault),
            44 => Ok(Self::HmacFatalFault),
            45 => Ok(Self::KmacRecovOperationErr),
            46 => Ok(Self::KmacFatalFaultErr),
            47 => Ok(Self::OtbnFatal),
            48 => Ok(Self::OtbnRecov),
            49 => Ok(Self::KeymgrRecovOperationErr),
            50 => Ok(Self::KeymgrFatalFaultErr),
            51 => Ok(Self::CsrngRecovAlert),
            52 => Ok(Self::CsrngFatalAlert),
            53 => Ok(Self::EntropySrcRecovAlert),
            54 => Ok(Self::EntropySrcFatalAlert),
            55 => Ok(Self::Edn0RecovAlert),
            56 => Ok(Self::Edn0FatalAlert),
            57 => Ok(Self::Edn1RecovAlert),
            58 => Ok(Self::Edn1FatalAlert),
            59 => Ok(Self::SramCtrlMainFatalError),
            60 => Ok(Self::RomCtrlFatal),
            61 => Ok(Self::RvCoreIbexFatalSwErr),
            62 => Ok(Self::RvCoreIbexRecovSwErr),
            63 => Ok(Self::RvCoreIbexFatalHwErr),
            64 => Ok(Self::RvCoreIbexRecovHwErr),
            _ => Err(val),
        }
    }
}

/// PLIC Interrupt Source to Peripheral Map
///
/// This array is a mapping from `PlicIrqId` to
/// `PlicPeripheral`.
pub const PLIC_INTERRUPT_FOR_PERIPHERAL: [PlicPeripheral; 185] = [
    // None -> PlicPeripheral::Unknown
    PlicPeripheral::Unknown,
    // Uart0TxWatermark -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxWatermark -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0TxEmpty -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxOverflow -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxFrameErr -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxBreakErr -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxTimeout -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart0RxParityErr -> PlicPeripheral::Uart0
    PlicPeripheral::Uart0,
    // Uart1TxWatermark -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxWatermark -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1TxEmpty -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxOverflow -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxFrameErr -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxBreakErr -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxTimeout -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart1RxParityErr -> PlicPeripheral::Uart1
    PlicPeripheral::Uart1,
    // Uart2TxWatermark -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxWatermark -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2TxEmpty -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxOverflow -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxFrameErr -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxBreakErr -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxTimeout -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart2RxParityErr -> PlicPeripheral::Uart2
    PlicPeripheral::Uart2,
    // Uart3TxWatermark -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxWatermark -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3TxEmpty -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxOverflow -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxFrameErr -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxBreakErr -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxTimeout -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // Uart3RxParityErr -> PlicPeripheral::Uart3
    PlicPeripheral::Uart3,
    // GpioGpio0 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio1 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio2 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio3 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio4 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio5 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio6 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio7 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio8 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio9 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio10 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio11 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio12 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio13 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio14 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio15 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio16 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio17 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio18 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio19 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio20 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio21 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio22 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio23 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio24 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio25 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio26 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio27 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio28 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio29 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio30 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // GpioGpio31 -> PlicPeripheral::Gpio
    PlicPeripheral::Gpio,
    // SpiDeviceGenericRxFull -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceGenericRxWatermark -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceGenericTxWatermark -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceGenericRxError -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceGenericRxOverflow -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceGenericTxUnderflow -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceUploadCmdfifoNotEmpty -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceUploadPayloadNotEmpty -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceUploadPayloadOverflow -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceReadbufWatermark -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceReadbufFlip -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // SpiDeviceTpmHeaderNotEmpty -> PlicPeripheral::SpiDevice
    PlicPeripheral::SpiDevice,
    // I2c0FmtThreshold -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0RxThreshold -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0FmtOverflow -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0RxOverflow -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0Nak -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0SclInterference -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0SdaInterference -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0StretchTimeout -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0SdaUnstable -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0CmdComplete -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0TxStretch -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0TxOverflow -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0AcqFull -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0UnexpStop -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c0HostTimeout -> PlicPeripheral::I2c0
    PlicPeripheral::I2c0,
    // I2c1FmtThreshold -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1RxThreshold -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1FmtOverflow -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1RxOverflow -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1Nak -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1SclInterference -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1SdaInterference -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1StretchTimeout -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1SdaUnstable -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1CmdComplete -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1TxStretch -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1TxOverflow -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1AcqFull -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1UnexpStop -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c1HostTimeout -> PlicPeripheral::I2c1
    PlicPeripheral::I2c1,
    // I2c2FmtThreshold -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2RxThreshold -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2FmtOverflow -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2RxOverflow -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2Nak -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2SclInterference -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2SdaInterference -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2StretchTimeout -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2SdaUnstable -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2CmdComplete -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2TxStretch -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2TxOverflow -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2AcqFull -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2UnexpStop -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // I2c2HostTimeout -> PlicPeripheral::I2c2
    PlicPeripheral::I2c2,
    // PattgenDoneCh0 -> PlicPeripheral::Pattgen
    PlicPeripheral::Pattgen,
    // PattgenDoneCh1 -> PlicPeripheral::Pattgen
    PlicPeripheral::Pattgen,
    // RvTimerTimerExpiredHart0Timer0 -> PlicPeripheral::RvTimer
    PlicPeripheral::RvTimer,
    // OtpCtrlOtpOperationDone -> PlicPeripheral::OtpCtrl
    PlicPeripheral::OtpCtrl,
    // OtpCtrlOtpError -> PlicPeripheral::OtpCtrl
    PlicPeripheral::OtpCtrl,
    // AlertHandlerClassa -> PlicPeripheral::AlertHandler
    PlicPeripheral::AlertHandler,
    // AlertHandlerClassb -> PlicPeripheral::AlertHandler
    PlicPeripheral::AlertHandler,
    // AlertHandlerClassc -> PlicPeripheral::AlertHandler
    PlicPeripheral::AlertHandler,
    // AlertHandlerClassd -> PlicPeripheral::AlertHandler
    PlicPeripheral::AlertHandler,
    // SpiHost0Error -> PlicPeripheral::SpiHost0
    PlicPeripheral::SpiHost0,
    // SpiHost0SpiEvent -> PlicPeripheral::SpiHost0
    PlicPeripheral::SpiHost0,
    // SpiHost1Error -> PlicPeripheral::SpiHost1
    PlicPeripheral::SpiHost1,
    // SpiHost1SpiEvent -> PlicPeripheral::SpiHost1
    PlicPeripheral::SpiHost1,
    // UsbdevPktReceived -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevPktSent -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevDisconnected -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevHostLost -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevLinkReset -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevLinkSuspend -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevLinkResume -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevAvEmpty -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevRxFull -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevAvOverflow -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevLinkInErr -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevRxCrcErr -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevRxPidErr -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevRxBitstuffErr -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevFrame -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevPowered -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // UsbdevLinkOutErr -> PlicPeripheral::Usbdev
    PlicPeripheral::Usbdev,
    // PwrmgrAonWakeup -> PlicPeripheral::PwrmgrAon
    PlicPeripheral::PwrmgrAon,
    // SysrstCtrlAonEventDetected -> PlicPeripheral::SysrstCtrlAon
    PlicPeripheral::SysrstCtrlAon,
    // AdcCtrlAonMatchDone -> PlicPeripheral::AdcCtrlAon
    PlicPeripheral::AdcCtrlAon,
    // AonTimerAonWkupTimerExpired -> PlicPeripheral::AonTimerAon
    PlicPeripheral::AonTimerAon,
    // AonTimerAonWdogTimerBark -> PlicPeripheral::AonTimerAon
    PlicPeripheral::AonTimerAon,
    // SensorCtrlIoStatusChange -> PlicPeripheral::SensorCtrl
    PlicPeripheral::SensorCtrl,
    // SensorCtrlInitStatusChange -> PlicPeripheral::SensorCtrl
    PlicPeripheral::SensorCtrl,
    // FlashCtrlProgEmpty -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // FlashCtrlProgLvl -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // FlashCtrlRdFull -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // FlashCtrlRdLvl -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // FlashCtrlOpDone -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // FlashCtrlCorrErr -> PlicPeripheral::FlashCtrl
    PlicPeripheral::FlashCtrl,
    // HmacHmacDone -> PlicPeripheral::Hmac
    PlicPeripheral::Hmac,
    // HmacFifoEmpty -> PlicPeripheral::Hmac
    PlicPeripheral::Hmac,
    // HmacHmacErr -> PlicPeripheral::Hmac
    PlicPeripheral::Hmac,
    // KmacKmacDone -> PlicPeripheral::Kmac
    PlicPeripheral::Kmac,
    // KmacFifoEmpty -> PlicPeripheral::Kmac
    PlicPeripheral::Kmac,
    // KmacKmacErr -> PlicPeripheral::Kmac
    PlicPeripheral::Kmac,
    // OtbnDone -> PlicPeripheral::Otbn
    PlicPeripheral::Otbn,
    // KeymgrOpDone -> PlicPeripheral::Keymgr
    PlicPeripheral::Keymgr,
    // CsrngCsCmdReqDone -> PlicPeripheral::Csrng
    PlicPeripheral::Csrng,
    // CsrngCsEntropyReq -> PlicPeripheral::Csrng
    PlicPeripheral::Csrng,
    // CsrngCsHwInstExc -> PlicPeripheral::Csrng
    PlicPeripheral::Csrng,
    // CsrngCsFatalErr -> PlicPeripheral::Csrng
    PlicPeripheral::Csrng,
    // EntropySrcEsEntropyValid -> PlicPeripheral::EntropySrc
    PlicPeripheral::EntropySrc,
    // EntropySrcEsHealthTestFailed -> PlicPeripheral::EntropySrc
    PlicPeripheral::EntropySrc,
    // EntropySrcEsObserveFifoReady -> PlicPeripheral::EntropySrc
    PlicPeripheral::EntropySrc,
    // EntropySrcEsFatalErr -> PlicPeripheral::EntropySrc
    PlicPeripheral::EntropySrc,
    // Edn0EdnCmdReqDone -> PlicPeripheral::Edn0
    PlicPeripheral::Edn0,
    // Edn0EdnFatalErr -> PlicPeripheral::Edn0
    PlicPeripheral::Edn0,
    // Edn1EdnCmdReqDone -> PlicPeripheral::Edn1
    PlicPeripheral::Edn1,
    // Edn1EdnFatalErr -> PlicPeripheral::Edn1
    PlicPeripheral::Edn1,
];

/// Alert Handler Alert Source to Peripheral Map
///
/// This array is a mapping from `AlertId` to
/// `AlertPeripheral`.
pub const ALERT_FOR_PERIPHERAL: [AlertPeripheral; 65] = [
    // Uart0FatalFault -> AlertPeripheral::Uart0
    AlertPeripheral::Uart0,
    // Uart1FatalFault -> AlertPeripheral::Uart1
    AlertPeripheral::Uart1,
    // Uart2FatalFault -> AlertPeripheral::Uart2
    AlertPeripheral::Uart2,
    // Uart3FatalFault -> AlertPeripheral::Uart3
    AlertPeripheral::Uart3,
    // GpioFatalFault -> AlertPeripheral::Gpio
    AlertPeripheral::Gpio,
    // SpiDeviceFatalFault -> AlertPeripheral::SpiDevice
    AlertPeripheral::SpiDevice,
    // I2c0FatalFault -> AlertPeripheral::I2c0
    AlertPeripheral::I2c0,
    // I2c1FatalFault -> AlertPeripheral::I2c1
    AlertPeripheral::I2c1,
    // I2c2FatalFault -> AlertPeripheral::I2c2
    AlertPeripheral::I2c2,
    // PattgenFatalFault -> AlertPeripheral::Pattgen
    AlertPeripheral::Pattgen,
    // RvTimerFatalFault -> AlertPeripheral::RvTimer
    AlertPeripheral::RvTimer,
    // OtpCtrlFatalMacroError -> AlertPeripheral::OtpCtrl
    AlertPeripheral::OtpCtrl,
    // OtpCtrlFatalCheckError -> AlertPeripheral::OtpCtrl
    AlertPeripheral::OtpCtrl,
    // OtpCtrlFatalBusIntegError -> AlertPeripheral::OtpCtrl
    AlertPeripheral::OtpCtrl,
    // OtpCtrlFatalPrimOtpAlert -> AlertPeripheral::OtpCtrl
    AlertPeripheral::OtpCtrl,
    // OtpCtrlRecovPrimOtpAlert -> AlertPeripheral::OtpCtrl
    AlertPeripheral::OtpCtrl,
    // LcCtrlFatalProgError -> AlertPeripheral::LcCtrl
    AlertPeripheral::LcCtrl,
    // LcCtrlFatalStateError -> AlertPeripheral::LcCtrl
    AlertPeripheral::LcCtrl,
    // LcCtrlFatalBusIntegError -> AlertPeripheral::LcCtrl
    AlertPeripheral::LcCtrl,
    // SpiHost0FatalFault -> AlertPeripheral::SpiHost0
    AlertPeripheral::SpiHost0,
    // SpiHost1FatalFault -> AlertPeripheral::SpiHost1
    AlertPeripheral::SpiHost1,
    // UsbdevFatalFault -> AlertPeripheral::Usbdev
    AlertPeripheral::Usbdev,
    // PwrmgrAonFatalFault -> AlertPeripheral::PwrmgrAon
    AlertPeripheral::PwrmgrAon,
    // RstmgrAonFatalFault -> AlertPeripheral::RstmgrAon
    AlertPeripheral::RstmgrAon,
    // RstmgrAonFatalCnstyFault -> AlertPeripheral::RstmgrAon
    AlertPeripheral::RstmgrAon,
    // ClkmgrAonRecovFault -> AlertPeripheral::ClkmgrAon
    AlertPeripheral::ClkmgrAon,
    // ClkmgrAonFatalFault -> AlertPeripheral::ClkmgrAon
    AlertPeripheral::ClkmgrAon,
    // SysrstCtrlAonFatalFault -> AlertPeripheral::SysrstCtrlAon
    AlertPeripheral::SysrstCtrlAon,
    // AdcCtrlAonFatalFault -> AlertPeripheral::AdcCtrlAon
    AlertPeripheral::AdcCtrlAon,
    // PwmAonFatalFault -> AlertPeripheral::PwmAon
    AlertPeripheral::PwmAon,
    // PinmuxAonFatalFault -> AlertPeripheral::PinmuxAon
    AlertPeripheral::PinmuxAon,
    // AonTimerAonFatalFault -> AlertPeripheral::AonTimerAon
    AlertPeripheral::AonTimerAon,
    // SensorCtrlRecovAlert -> AlertPeripheral::SensorCtrl
    AlertPeripheral::SensorCtrl,
    // SensorCtrlFatalAlert -> AlertPeripheral::SensorCtrl
    AlertPeripheral::SensorCtrl,
    // SramCtrlRetAonFatalError -> AlertPeripheral::SramCtrlRetAon
    AlertPeripheral::SramCtrlRetAon,
    // FlashCtrlRecovErr -> AlertPeripheral::FlashCtrl
    AlertPeripheral::FlashCtrl,
    // FlashCtrlFatalStdErr -> AlertPeripheral::FlashCtrl
    AlertPeripheral::FlashCtrl,
    // FlashCtrlFatalErr -> AlertPeripheral::FlashCtrl
    AlertPeripheral::FlashCtrl,
    // FlashCtrlFatalPrimFlashAlert -> AlertPeripheral::FlashCtrl
    AlertPeripheral::FlashCtrl,
    // FlashCtrlRecovPrimFlashAlert -> AlertPeripheral::FlashCtrl
    AlertPeripheral::FlashCtrl,
    // RvDmFatalFault -> AlertPeripheral::RvDm
    AlertPeripheral::RvDm,
    // RvPlicFatalFault -> AlertPeripheral::RvPlic
    AlertPeripheral::RvPlic,
    // AesRecovCtrlUpdateErr -> AlertPeripheral::Aes
    AlertPeripheral::Aes,
    // AesFatalFault -> AlertPeripheral::Aes
    AlertPeripheral::Aes,
    // HmacFatalFault -> AlertPeripheral::Hmac
    AlertPeripheral::Hmac,
    // KmacRecovOperationErr -> AlertPeripheral::Kmac
    AlertPeripheral::Kmac,
    // KmacFatalFaultErr -> AlertPeripheral::Kmac
    AlertPeripheral::Kmac,
    // OtbnFatal -> AlertPeripheral::Otbn
    AlertPeripheral::Otbn,
    // OtbnRecov -> AlertPeripheral::Otbn
    AlertPeripheral::Otbn,
    // KeymgrRecovOperationErr -> AlertPeripheral::Keymgr
    AlertPeripheral::Keymgr,
    // KeymgrFatalFaultErr -> AlertPeripheral::Keymgr
    AlertPeripheral::Keymgr,
    // CsrngRecovAlert -> AlertPeripheral::Csrng
    AlertPeripheral::Csrng,
    // CsrngFatalAlert -> AlertPeripheral::Csrng
    AlertPeripheral::Csrng,
    // EntropySrcRecovAlert -> AlertPeripheral::EntropySrc
    AlertPeripheral::EntropySrc,
    // EntropySrcFatalAlert -> AlertPeripheral::EntropySrc
    AlertPeripheral::EntropySrc,
    // Edn0RecovAlert -> AlertPeripheral::Edn0
    AlertPeripheral::Edn0,
    // Edn0FatalAlert -> AlertPeripheral::Edn0
    AlertPeripheral::Edn0,
    // Edn1RecovAlert -> AlertPeripheral::Edn1
    AlertPeripheral::Edn1,
    // Edn1FatalAlert -> AlertPeripheral::Edn1
    AlertPeripheral::Edn1,
    // SramCtrlMainFatalError -> AlertPeripheral::SramCtrlMain
    AlertPeripheral::SramCtrlMain,
    // RomCtrlFatal -> AlertPeripheral::RomCtrl
    AlertPeripheral::RomCtrl,
    // RvCoreIbexFatalSwErr -> AlertPeripheral::RvCoreIbex
    AlertPeripheral::RvCoreIbex,
    // RvCoreIbexRecovSwErr -> AlertPeripheral::RvCoreIbex
    AlertPeripheral::RvCoreIbex,
    // RvCoreIbexFatalHwErr -> AlertPeripheral::RvCoreIbex
    AlertPeripheral::RvCoreIbex,
    // RvCoreIbexRecovHwErr -> AlertPeripheral::RvCoreIbex
    AlertPeripheral::RvCoreIbex,
];

// PERIPH_INSEL ranges from 0 to NUM_MIO_PADS + 2 -1}
//  0 and 1 are tied to value 0 and 1
pub const NUM_MIO_PADS: usize = 47;
pub const NUM_DIO_PADS: usize = 16;

pub const PINMUX_MIO_PERIPH_INSEL_IDX_OFFSET: usize = 2;
pub const PINMUX_PERIPH_OUTSEL_IDX_OFFSET: usize = 3;

/// Pinmux Peripheral Input.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PinmuxPeripheralIn {
    /// Peripheral Input 0
    GpioGpio0 = 0,
    /// Peripheral Input 1
    GpioGpio1 = 1,
    /// Peripheral Input 2
    GpioGpio2 = 2,
    /// Peripheral Input 3
    GpioGpio3 = 3,
    /// Peripheral Input 4
    GpioGpio4 = 4,
    /// Peripheral Input 5
    GpioGpio5 = 5,
    /// Peripheral Input 6
    GpioGpio6 = 6,
    /// Peripheral Input 7
    GpioGpio7 = 7,
    /// Peripheral Input 8
    GpioGpio8 = 8,
    /// Peripheral Input 9
    GpioGpio9 = 9,
    /// Peripheral Input 10
    GpioGpio10 = 10,
    /// Peripheral Input 11
    GpioGpio11 = 11,
    /// Peripheral Input 12
    GpioGpio12 = 12,
    /// Peripheral Input 13
    GpioGpio13 = 13,
    /// Peripheral Input 14
    GpioGpio14 = 14,
    /// Peripheral Input 15
    GpioGpio15 = 15,
    /// Peripheral Input 16
    GpioGpio16 = 16,
    /// Peripheral Input 17
    GpioGpio17 = 17,
    /// Peripheral Input 18
    GpioGpio18 = 18,
    /// Peripheral Input 19
    GpioGpio19 = 19,
    /// Peripheral Input 20
    GpioGpio20 = 20,
    /// Peripheral Input 21
    GpioGpio21 = 21,
    /// Peripheral Input 22
    GpioGpio22 = 22,
    /// Peripheral Input 23
    GpioGpio23 = 23,
    /// Peripheral Input 24
    GpioGpio24 = 24,
    /// Peripheral Input 25
    GpioGpio25 = 25,
    /// Peripheral Input 26
    GpioGpio26 = 26,
    /// Peripheral Input 27
    GpioGpio27 = 27,
    /// Peripheral Input 28
    GpioGpio28 = 28,
    /// Peripheral Input 29
    GpioGpio29 = 29,
    /// Peripheral Input 30
    GpioGpio30 = 30,
    /// Peripheral Input 31
    GpioGpio31 = 31,
    /// Peripheral Input 32
    I2c0Sda = 32,
    /// Peripheral Input 33
    I2c0Scl = 33,
    /// Peripheral Input 34
    I2c1Sda = 34,
    /// Peripheral Input 35
    I2c1Scl = 35,
    /// Peripheral Input 36
    I2c2Sda = 36,
    /// Peripheral Input 37
    I2c2Scl = 37,
    /// Peripheral Input 38
    SpiHost1Sd0 = 38,
    /// Peripheral Input 39
    SpiHost1Sd1 = 39,
    /// Peripheral Input 40
    SpiHost1Sd2 = 40,
    /// Peripheral Input 41
    SpiHost1Sd3 = 41,
    /// Peripheral Input 42
    Uart0Rx = 42,
    /// Peripheral Input 43
    Uart1Rx = 43,
    /// Peripheral Input 44
    Uart2Rx = 44,
    /// Peripheral Input 45
    Uart3Rx = 45,
    /// Peripheral Input 46
    SpiDeviceTpmCsb = 46,
    /// Peripheral Input 47
    FlashCtrlTck = 47,
    /// Peripheral Input 48
    FlashCtrlTms = 48,
    /// Peripheral Input 49
    FlashCtrlTdi = 49,
    /// Peripheral Input 50
    SysrstCtrlAonAcPresent = 50,
    /// Peripheral Input 51
    SysrstCtrlAonKey0In = 51,
    /// Peripheral Input 52
    SysrstCtrlAonKey1In = 52,
    /// Peripheral Input 53
    SysrstCtrlAonKey2In = 53,
    /// Peripheral Input 54
    SysrstCtrlAonPwrbIn = 54,
    /// Peripheral Input 55
    SysrstCtrlAonLidOpen = 55,
    /// Peripheral Input 56
    UsbdevSense = 56,
}

impl TryFrom<u32> for PinmuxPeripheralIn {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::GpioGpio0),
            1 => Ok(Self::GpioGpio1),
            2 => Ok(Self::GpioGpio2),
            3 => Ok(Self::GpioGpio3),
            4 => Ok(Self::GpioGpio4),
            5 => Ok(Self::GpioGpio5),
            6 => Ok(Self::GpioGpio6),
            7 => Ok(Self::GpioGpio7),
            8 => Ok(Self::GpioGpio8),
            9 => Ok(Self::GpioGpio9),
            10 => Ok(Self::GpioGpio10),
            11 => Ok(Self::GpioGpio11),
            12 => Ok(Self::GpioGpio12),
            13 => Ok(Self::GpioGpio13),
            14 => Ok(Self::GpioGpio14),
            15 => Ok(Self::GpioGpio15),
            16 => Ok(Self::GpioGpio16),
            17 => Ok(Self::GpioGpio17),
            18 => Ok(Self::GpioGpio18),
            19 => Ok(Self::GpioGpio19),
            20 => Ok(Self::GpioGpio20),
            21 => Ok(Self::GpioGpio21),
            22 => Ok(Self::GpioGpio22),
            23 => Ok(Self::GpioGpio23),
            24 => Ok(Self::GpioGpio24),
            25 => Ok(Self::GpioGpio25),
            26 => Ok(Self::GpioGpio26),
            27 => Ok(Self::GpioGpio27),
            28 => Ok(Self::GpioGpio28),
            29 => Ok(Self::GpioGpio29),
            30 => Ok(Self::GpioGpio30),
            31 => Ok(Self::GpioGpio31),
            32 => Ok(Self::I2c0Sda),
            33 => Ok(Self::I2c0Scl),
            34 => Ok(Self::I2c1Sda),
            35 => Ok(Self::I2c1Scl),
            36 => Ok(Self::I2c2Sda),
            37 => Ok(Self::I2c2Scl),
            38 => Ok(Self::SpiHost1Sd0),
            39 => Ok(Self::SpiHost1Sd1),
            40 => Ok(Self::SpiHost1Sd2),
            41 => Ok(Self::SpiHost1Sd3),
            42 => Ok(Self::Uart0Rx),
            43 => Ok(Self::Uart1Rx),
            44 => Ok(Self::Uart2Rx),
            45 => Ok(Self::Uart3Rx),
            46 => Ok(Self::SpiDeviceTpmCsb),
            47 => Ok(Self::FlashCtrlTck),
            48 => Ok(Self::FlashCtrlTms),
            49 => Ok(Self::FlashCtrlTdi),
            50 => Ok(Self::SysrstCtrlAonAcPresent),
            51 => Ok(Self::SysrstCtrlAonKey0In),
            52 => Ok(Self::SysrstCtrlAonKey1In),
            53 => Ok(Self::SysrstCtrlAonKey2In),
            54 => Ok(Self::SysrstCtrlAonPwrbIn),
            55 => Ok(Self::SysrstCtrlAonLidOpen),
            56 => Ok(Self::UsbdevSense),
            _ => Err(val),
        }
    }
}

/// Pinmux MIO Input Selector.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PinmuxInsel {
    /// Tie constantly to zero
    ConstantZero = 0,
    /// Tie constantly to one
    ConstantOne = 1,
    /// MIO Pad 0
    Ioa0 = 2,
    /// MIO Pad 1
    Ioa1 = 3,
    /// MIO Pad 2
    Ioa2 = 4,
    /// MIO Pad 3
    Ioa3 = 5,
    /// MIO Pad 4
    Ioa4 = 6,
    /// MIO Pad 5
    Ioa5 = 7,
    /// MIO Pad 6
    Ioa6 = 8,
    /// MIO Pad 7
    Ioa7 = 9,
    /// MIO Pad 8
    Ioa8 = 10,
    /// MIO Pad 9
    Iob0 = 11,
    /// MIO Pad 10
    Iob1 = 12,
    /// MIO Pad 11
    Iob2 = 13,
    /// MIO Pad 12
    Iob3 = 14,
    /// MIO Pad 13
    Iob4 = 15,
    /// MIO Pad 14
    Iob5 = 16,
    /// MIO Pad 15
    Iob6 = 17,
    /// MIO Pad 16
    Iob7 = 18,
    /// MIO Pad 17
    Iob8 = 19,
    /// MIO Pad 18
    Iob9 = 20,
    /// MIO Pad 19
    Iob10 = 21,
    /// MIO Pad 20
    Iob11 = 22,
    /// MIO Pad 21
    Iob12 = 23,
    /// MIO Pad 22
    Ioc0 = 24,
    /// MIO Pad 23
    Ioc1 = 25,
    /// MIO Pad 24
    Ioc2 = 26,
    /// MIO Pad 25
    Ioc3 = 27,
    /// MIO Pad 26
    Ioc4 = 28,
    /// MIO Pad 27
    Ioc5 = 29,
    /// MIO Pad 28
    Ioc6 = 30,
    /// MIO Pad 29
    Ioc7 = 31,
    /// MIO Pad 30
    Ioc8 = 32,
    /// MIO Pad 31
    Ioc9 = 33,
    /// MIO Pad 32
    Ioc10 = 34,
    /// MIO Pad 33
    Ioc11 = 35,
    /// MIO Pad 34
    Ioc12 = 36,
    /// MIO Pad 35
    Ior0 = 37,
    /// MIO Pad 36
    Ior1 = 38,
    /// MIO Pad 37
    Ior2 = 39,
    /// MIO Pad 38
    Ior3 = 40,
    /// MIO Pad 39
    Ior4 = 41,
    /// MIO Pad 40
    Ior5 = 42,
    /// MIO Pad 41
    Ior6 = 43,
    /// MIO Pad 42
    Ior7 = 44,
    /// MIO Pad 43
    Ior10 = 45,
    /// MIO Pad 44
    Ior11 = 46,
    /// MIO Pad 45
    Ior12 = 47,
    /// MIO Pad 46
    Ior13 = 48,
}

impl TryFrom<u32> for PinmuxInsel {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::ConstantZero),
            1 => Ok(Self::ConstantOne),
            2 => Ok(Self::Ioa0),
            3 => Ok(Self::Ioa1),
            4 => Ok(Self::Ioa2),
            5 => Ok(Self::Ioa3),
            6 => Ok(Self::Ioa4),
            7 => Ok(Self::Ioa5),
            8 => Ok(Self::Ioa6),
            9 => Ok(Self::Ioa7),
            10 => Ok(Self::Ioa8),
            11 => Ok(Self::Iob0),
            12 => Ok(Self::Iob1),
            13 => Ok(Self::Iob2),
            14 => Ok(Self::Iob3),
            15 => Ok(Self::Iob4),
            16 => Ok(Self::Iob5),
            17 => Ok(Self::Iob6),
            18 => Ok(Self::Iob7),
            19 => Ok(Self::Iob8),
            20 => Ok(Self::Iob9),
            21 => Ok(Self::Iob10),
            22 => Ok(Self::Iob11),
            23 => Ok(Self::Iob12),
            24 => Ok(Self::Ioc0),
            25 => Ok(Self::Ioc1),
            26 => Ok(Self::Ioc2),
            27 => Ok(Self::Ioc3),
            28 => Ok(Self::Ioc4),
            29 => Ok(Self::Ioc5),
            30 => Ok(Self::Ioc6),
            31 => Ok(Self::Ioc7),
            32 => Ok(Self::Ioc8),
            33 => Ok(Self::Ioc9),
            34 => Ok(Self::Ioc10),
            35 => Ok(Self::Ioc11),
            36 => Ok(Self::Ioc12),
            37 => Ok(Self::Ior0),
            38 => Ok(Self::Ior1),
            39 => Ok(Self::Ior2),
            40 => Ok(Self::Ior3),
            41 => Ok(Self::Ior4),
            42 => Ok(Self::Ior5),
            43 => Ok(Self::Ior6),
            44 => Ok(Self::Ior7),
            45 => Ok(Self::Ior10),
            46 => Ok(Self::Ior11),
            47 => Ok(Self::Ior12),
            48 => Ok(Self::Ior13),
            _ => Err(val),
        }
    }
}

/// Pinmux MIO Output.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PinmuxMioOut {
    /// MIO Pad 0
    Ioa0 = 0,
    /// MIO Pad 1
    Ioa1 = 1,
    /// MIO Pad 2
    Ioa2 = 2,
    /// MIO Pad 3
    Ioa3 = 3,
    /// MIO Pad 4
    Ioa4 = 4,
    /// MIO Pad 5
    Ioa5 = 5,
    /// MIO Pad 6
    Ioa6 = 6,
    /// MIO Pad 7
    Ioa7 = 7,
    /// MIO Pad 8
    Ioa8 = 8,
    /// MIO Pad 9
    Iob0 = 9,
    /// MIO Pad 10
    Iob1 = 10,
    /// MIO Pad 11
    Iob2 = 11,
    /// MIO Pad 12
    Iob3 = 12,
    /// MIO Pad 13
    Iob4 = 13,
    /// MIO Pad 14
    Iob5 = 14,
    /// MIO Pad 15
    Iob6 = 15,
    /// MIO Pad 16
    Iob7 = 16,
    /// MIO Pad 17
    Iob8 = 17,
    /// MIO Pad 18
    Iob9 = 18,
    /// MIO Pad 19
    Iob10 = 19,
    /// MIO Pad 20
    Iob11 = 20,
    /// MIO Pad 21
    Iob12 = 21,
    /// MIO Pad 22
    Ioc0 = 22,
    /// MIO Pad 23
    Ioc1 = 23,
    /// MIO Pad 24
    Ioc2 = 24,
    /// MIO Pad 25
    Ioc3 = 25,
    /// MIO Pad 26
    Ioc4 = 26,
    /// MIO Pad 27
    Ioc5 = 27,
    /// MIO Pad 28
    Ioc6 = 28,
    /// MIO Pad 29
    Ioc7 = 29,
    /// MIO Pad 30
    Ioc8 = 30,
    /// MIO Pad 31
    Ioc9 = 31,
    /// MIO Pad 32
    Ioc10 = 32,
    /// MIO Pad 33
    Ioc11 = 33,
    /// MIO Pad 34
    Ioc12 = 34,
    /// MIO Pad 35
    Ior0 = 35,
    /// MIO Pad 36
    Ior1 = 36,
    /// MIO Pad 37
    Ior2 = 37,
    /// MIO Pad 38
    Ior3 = 38,
    /// MIO Pad 39
    Ior4 = 39,
    /// MIO Pad 40
    Ior5 = 40,
    /// MIO Pad 41
    Ior6 = 41,
    /// MIO Pad 42
    Ior7 = 42,
    /// MIO Pad 43
    Ior10 = 43,
    /// MIO Pad 44
    Ior11 = 44,
    /// MIO Pad 45
    Ior12 = 45,
    /// MIO Pad 46
    Ior13 = 46,
}

impl TryFrom<u32> for PinmuxMioOut {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::Ioa0),
            1 => Ok(Self::Ioa1),
            2 => Ok(Self::Ioa2),
            3 => Ok(Self::Ioa3),
            4 => Ok(Self::Ioa4),
            5 => Ok(Self::Ioa5),
            6 => Ok(Self::Ioa6),
            7 => Ok(Self::Ioa7),
            8 => Ok(Self::Ioa8),
            9 => Ok(Self::Iob0),
            10 => Ok(Self::Iob1),
            11 => Ok(Self::Iob2),
            12 => Ok(Self::Iob3),
            13 => Ok(Self::Iob4),
            14 => Ok(Self::Iob5),
            15 => Ok(Self::Iob6),
            16 => Ok(Self::Iob7),
            17 => Ok(Self::Iob8),
            18 => Ok(Self::Iob9),
            19 => Ok(Self::Iob10),
            20 => Ok(Self::Iob11),
            21 => Ok(Self::Iob12),
            22 => Ok(Self::Ioc0),
            23 => Ok(Self::Ioc1),
            24 => Ok(Self::Ioc2),
            25 => Ok(Self::Ioc3),
            26 => Ok(Self::Ioc4),
            27 => Ok(Self::Ioc5),
            28 => Ok(Self::Ioc6),
            29 => Ok(Self::Ioc7),
            30 => Ok(Self::Ioc8),
            31 => Ok(Self::Ioc9),
            32 => Ok(Self::Ioc10),
            33 => Ok(Self::Ioc11),
            34 => Ok(Self::Ioc12),
            35 => Ok(Self::Ior0),
            36 => Ok(Self::Ior1),
            37 => Ok(Self::Ior2),
            38 => Ok(Self::Ior3),
            39 => Ok(Self::Ior4),
            40 => Ok(Self::Ior5),
            41 => Ok(Self::Ior6),
            42 => Ok(Self::Ior7),
            43 => Ok(Self::Ior10),
            44 => Ok(Self::Ior11),
            45 => Ok(Self::Ior12),
            46 => Ok(Self::Ior13),
            _ => Err(val),
        }
    }
}

/// Pinmux Peripheral Output Selector.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PinmuxOutsel {
    /// Tie constantly to zero
    ConstantZero = 0,
    /// Tie constantly to one
    ConstantOne = 1,
    /// Tie constantly to high-Z
    ConstantHighZ = 2,
    /// Peripheral Output 0
    GpioGpio0 = 3,
    /// Peripheral Output 1
    GpioGpio1 = 4,
    /// Peripheral Output 2
    GpioGpio2 = 5,
    /// Peripheral Output 3
    GpioGpio3 = 6,
    /// Peripheral Output 4
    GpioGpio4 = 7,
    /// Peripheral Output 5
    GpioGpio5 = 8,
    /// Peripheral Output 6
    GpioGpio6 = 9,
    /// Peripheral Output 7
    GpioGpio7 = 10,
    /// Peripheral Output 8
    GpioGpio8 = 11,
    /// Peripheral Output 9
    GpioGpio9 = 12,
    /// Peripheral Output 10
    GpioGpio10 = 13,
    /// Peripheral Output 11
    GpioGpio11 = 14,
    /// Peripheral Output 12
    GpioGpio12 = 15,
    /// Peripheral Output 13
    GpioGpio13 = 16,
    /// Peripheral Output 14
    GpioGpio14 = 17,
    /// Peripheral Output 15
    GpioGpio15 = 18,
    /// Peripheral Output 16
    GpioGpio16 = 19,
    /// Peripheral Output 17
    GpioGpio17 = 20,
    /// Peripheral Output 18
    GpioGpio18 = 21,
    /// Peripheral Output 19
    GpioGpio19 = 22,
    /// Peripheral Output 20
    GpioGpio20 = 23,
    /// Peripheral Output 21
    GpioGpio21 = 24,
    /// Peripheral Output 22
    GpioGpio22 = 25,
    /// Peripheral Output 23
    GpioGpio23 = 26,
    /// Peripheral Output 24
    GpioGpio24 = 27,
    /// Peripheral Output 25
    GpioGpio25 = 28,
    /// Peripheral Output 26
    GpioGpio26 = 29,
    /// Peripheral Output 27
    GpioGpio27 = 30,
    /// Peripheral Output 28
    GpioGpio28 = 31,
    /// Peripheral Output 29
    GpioGpio29 = 32,
    /// Peripheral Output 30
    GpioGpio30 = 33,
    /// Peripheral Output 31
    GpioGpio31 = 34,
    /// Peripheral Output 32
    I2c0Sda = 35,
    /// Peripheral Output 33
    I2c0Scl = 36,
    /// Peripheral Output 34
    I2c1Sda = 37,
    /// Peripheral Output 35
    I2c1Scl = 38,
    /// Peripheral Output 36
    I2c2Sda = 39,
    /// Peripheral Output 37
    I2c2Scl = 40,
    /// Peripheral Output 38
    SpiHost1Sd0 = 41,
    /// Peripheral Output 39
    SpiHost1Sd1 = 42,
    /// Peripheral Output 40
    SpiHost1Sd2 = 43,
    /// Peripheral Output 41
    SpiHost1Sd3 = 44,
    /// Peripheral Output 42
    Uart0Tx = 45,
    /// Peripheral Output 43
    Uart1Tx = 46,
    /// Peripheral Output 44
    Uart2Tx = 47,
    /// Peripheral Output 45
    Uart3Tx = 48,
    /// Peripheral Output 46
    PattgenPda0Tx = 49,
    /// Peripheral Output 47
    PattgenPcl0Tx = 50,
    /// Peripheral Output 48
    PattgenPda1Tx = 51,
    /// Peripheral Output 49
    PattgenPcl1Tx = 52,
    /// Peripheral Output 50
    SpiHost1Sck = 53,
    /// Peripheral Output 51
    SpiHost1Csb = 54,
    /// Peripheral Output 52
    FlashCtrlTdo = 55,
    /// Peripheral Output 53
    SensorCtrlAstDebugOut0 = 56,
    /// Peripheral Output 54
    SensorCtrlAstDebugOut1 = 57,
    /// Peripheral Output 55
    SensorCtrlAstDebugOut2 = 58,
    /// Peripheral Output 56
    SensorCtrlAstDebugOut3 = 59,
    /// Peripheral Output 57
    SensorCtrlAstDebugOut4 = 60,
    /// Peripheral Output 58
    SensorCtrlAstDebugOut5 = 61,
    /// Peripheral Output 59
    SensorCtrlAstDebugOut6 = 62,
    /// Peripheral Output 60
    SensorCtrlAstDebugOut7 = 63,
    /// Peripheral Output 61
    SensorCtrlAstDebugOut8 = 64,
    /// Peripheral Output 62
    PwmAonPwm0 = 65,
    /// Peripheral Output 63
    PwmAonPwm1 = 66,
    /// Peripheral Output 64
    PwmAonPwm2 = 67,
    /// Peripheral Output 65
    PwmAonPwm3 = 68,
    /// Peripheral Output 66
    PwmAonPwm4 = 69,
    /// Peripheral Output 67
    PwmAonPwm5 = 70,
    /// Peripheral Output 68
    OtpCtrlTest0 = 71,
    /// Peripheral Output 69
    SysrstCtrlAonBatDisable = 72,
    /// Peripheral Output 70
    SysrstCtrlAonKey0Out = 73,
    /// Peripheral Output 71
    SysrstCtrlAonKey1Out = 74,
    /// Peripheral Output 72
    SysrstCtrlAonKey2Out = 75,
    /// Peripheral Output 73
    SysrstCtrlAonPwrbOut = 76,
    /// Peripheral Output 74
    SysrstCtrlAonZ3Wakeup = 77,
}

impl TryFrom<u32> for PinmuxOutsel {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::ConstantZero),
            1 => Ok(Self::ConstantOne),
            2 => Ok(Self::ConstantHighZ),
            3 => Ok(Self::GpioGpio0),
            4 => Ok(Self::GpioGpio1),
            5 => Ok(Self::GpioGpio2),
            6 => Ok(Self::GpioGpio3),
            7 => Ok(Self::GpioGpio4),
            8 => Ok(Self::GpioGpio5),
            9 => Ok(Self::GpioGpio6),
            10 => Ok(Self::GpioGpio7),
            11 => Ok(Self::GpioGpio8),
            12 => Ok(Self::GpioGpio9),
            13 => Ok(Self::GpioGpio10),
            14 => Ok(Self::GpioGpio11),
            15 => Ok(Self::GpioGpio12),
            16 => Ok(Self::GpioGpio13),
            17 => Ok(Self::GpioGpio14),
            18 => Ok(Self::GpioGpio15),
            19 => Ok(Self::GpioGpio16),
            20 => Ok(Self::GpioGpio17),
            21 => Ok(Self::GpioGpio18),
            22 => Ok(Self::GpioGpio19),
            23 => Ok(Self::GpioGpio20),
            24 => Ok(Self::GpioGpio21),
            25 => Ok(Self::GpioGpio22),
            26 => Ok(Self::GpioGpio23),
            27 => Ok(Self::GpioGpio24),
            28 => Ok(Self::GpioGpio25),
            29 => Ok(Self::GpioGpio26),
            30 => Ok(Self::GpioGpio27),
            31 => Ok(Self::GpioGpio28),
            32 => Ok(Self::GpioGpio29),
            33 => Ok(Self::GpioGpio30),
            34 => Ok(Self::GpioGpio31),
            35 => Ok(Self::I2c0Sda),
            36 => Ok(Self::I2c0Scl),
            37 => Ok(Self::I2c1Sda),
            38 => Ok(Self::I2c1Scl),
            39 => Ok(Self::I2c2Sda),
            40 => Ok(Self::I2c2Scl),
            41 => Ok(Self::SpiHost1Sd0),
            42 => Ok(Self::SpiHost1Sd1),
            43 => Ok(Self::SpiHost1Sd2),
            44 => Ok(Self::SpiHost1Sd3),
            45 => Ok(Self::Uart0Tx),
            46 => Ok(Self::Uart1Tx),
            47 => Ok(Self::Uart2Tx),
            48 => Ok(Self::Uart3Tx),
            49 => Ok(Self::PattgenPda0Tx),
            50 => Ok(Self::PattgenPcl0Tx),
            51 => Ok(Self::PattgenPda1Tx),
            52 => Ok(Self::PattgenPcl1Tx),
            53 => Ok(Self::SpiHost1Sck),
            54 => Ok(Self::SpiHost1Csb),
            55 => Ok(Self::FlashCtrlTdo),
            56 => Ok(Self::SensorCtrlAstDebugOut0),
            57 => Ok(Self::SensorCtrlAstDebugOut1),
            58 => Ok(Self::SensorCtrlAstDebugOut2),
            59 => Ok(Self::SensorCtrlAstDebugOut3),
            60 => Ok(Self::SensorCtrlAstDebugOut4),
            61 => Ok(Self::SensorCtrlAstDebugOut5),
            62 => Ok(Self::SensorCtrlAstDebugOut6),
            63 => Ok(Self::SensorCtrlAstDebugOut7),
            64 => Ok(Self::SensorCtrlAstDebugOut8),
            65 => Ok(Self::PwmAonPwm0),
            66 => Ok(Self::PwmAonPwm1),
            67 => Ok(Self::PwmAonPwm2),
            68 => Ok(Self::PwmAonPwm3),
            69 => Ok(Self::PwmAonPwm4),
            70 => Ok(Self::PwmAonPwm5),
            71 => Ok(Self::OtpCtrlTest0),
            72 => Ok(Self::SysrstCtrlAonBatDisable),
            73 => Ok(Self::SysrstCtrlAonKey0Out),
            74 => Ok(Self::SysrstCtrlAonKey1Out),
            75 => Ok(Self::SysrstCtrlAonKey2Out),
            76 => Ok(Self::SysrstCtrlAonPwrbOut),
            77 => Ok(Self::SysrstCtrlAonZ3Wakeup),
            _ => Err(val),
        }
    }
}

/// Dedicated Pad Selects
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum DirectPads {
    UsbdevUsbDp = 0,
    UsbdevUsbDn = 1,
    SpiHost0Sd0 = 2,
    SpiHost0Sd1 = 3,
    SpiHost0Sd2 = 4,
    SpiHost0Sd3 = 5,
    SpiDeviceSd0 = 6,
    SpiDeviceSd1 = 7,
    SpiDeviceSd2 = 8,
    SpiDeviceSd3 = 9,
    SysrstCtrlAonEcRstL = 10,
    SysrstCtrlAonFlashWpL = 11,
    SpiDeviceSck = 12,
    SpiDeviceCsb = 13,
    SpiHost0Sck = 14,
    SpiHost0Csb = 15,
}

impl TryFrom<u32> for DirectPads {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::UsbdevUsbDp),
            1 => Ok(Self::UsbdevUsbDn),
            2 => Ok(Self::SpiHost0Sd0),
            3 => Ok(Self::SpiHost0Sd1),
            4 => Ok(Self::SpiHost0Sd2),
            5 => Ok(Self::SpiHost0Sd3),
            6 => Ok(Self::SpiDeviceSd0),
            7 => Ok(Self::SpiDeviceSd1),
            8 => Ok(Self::SpiDeviceSd2),
            9 => Ok(Self::SpiDeviceSd3),
            10 => Ok(Self::SysrstCtrlAonEcRstL),
            11 => Ok(Self::SysrstCtrlAonFlashWpL),
            12 => Ok(Self::SpiDeviceSck),
            13 => Ok(Self::SpiDeviceCsb),
            14 => Ok(Self::SpiHost0Sck),
            15 => Ok(Self::SpiHost0Csb),
            _ => Err(val),
        }
    }
}

/// Muxed Pad Selects
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum MuxedPads {
    Ioa0 = 0,
    Ioa1 = 1,
    Ioa2 = 2,
    Ioa3 = 3,
    Ioa4 = 4,
    Ioa5 = 5,
    Ioa6 = 6,
    Ioa7 = 7,
    Ioa8 = 8,
    Iob0 = 9,
    Iob1 = 10,
    Iob2 = 11,
    Iob3 = 12,
    Iob4 = 13,
    Iob5 = 14,
    Iob6 = 15,
    Iob7 = 16,
    Iob8 = 17,
    Iob9 = 18,
    Iob10 = 19,
    Iob11 = 20,
    Iob12 = 21,
    Ioc0 = 22,
    Ioc1 = 23,
    Ioc2 = 24,
    Ioc3 = 25,
    Ioc4 = 26,
    Ioc5 = 27,
    Ioc6 = 28,
    Ioc7 = 29,
    Ioc8 = 30,
    Ioc9 = 31,
    Ioc10 = 32,
    Ioc11 = 33,
    Ioc12 = 34,
    Ior0 = 35,
    Ior1 = 36,
    Ior2 = 37,
    Ior3 = 38,
    Ior4 = 39,
    Ior5 = 40,
    Ior6 = 41,
    Ior7 = 42,
    Ior10 = 43,
    Ior11 = 44,
    Ior12 = 45,
    Ior13 = 46,
}

impl TryFrom<u32> for MuxedPads {
    type Error = u32;
    fn try_from(val: u32) -> Result<Self, Self::Error> {
        match val {
            0 => Ok(Self::Ioa0),
            1 => Ok(Self::Ioa1),
            2 => Ok(Self::Ioa2),
            3 => Ok(Self::Ioa3),
            4 => Ok(Self::Ioa4),
            5 => Ok(Self::Ioa5),
            6 => Ok(Self::Ioa6),
            7 => Ok(Self::Ioa7),
            8 => Ok(Self::Ioa8),
            9 => Ok(Self::Iob0),
            10 => Ok(Self::Iob1),
            11 => Ok(Self::Iob2),
            12 => Ok(Self::Iob3),
            13 => Ok(Self::Iob4),
            14 => Ok(Self::Iob5),
            15 => Ok(Self::Iob6),
            16 => Ok(Self::Iob7),
            17 => Ok(Self::Iob8),
            18 => Ok(Self::Iob9),
            19 => Ok(Self::Iob10),
            20 => Ok(Self::Iob11),
            21 => Ok(Self::Iob12),
            22 => Ok(Self::Ioc0),
            23 => Ok(Self::Ioc1),
            24 => Ok(Self::Ioc2),
            25 => Ok(Self::Ioc3),
            26 => Ok(Self::Ioc4),
            27 => Ok(Self::Ioc5),
            28 => Ok(Self::Ioc6),
            29 => Ok(Self::Ioc7),
            30 => Ok(Self::Ioc8),
            31 => Ok(Self::Ioc9),
            32 => Ok(Self::Ioc10),
            33 => Ok(Self::Ioc11),
            34 => Ok(Self::Ioc12),
            35 => Ok(Self::Ior0),
            36 => Ok(Self::Ior1),
            37 => Ok(Self::Ior2),
            38 => Ok(Self::Ior3),
            39 => Ok(Self::Ior4),
            40 => Ok(Self::Ior5),
            41 => Ok(Self::Ior6),
            42 => Ok(Self::Ior7),
            43 => Ok(Self::Ior10),
            44 => Ok(Self::Ior11),
            45 => Ok(Self::Ior12),
            46 => Ok(Self::Ior13),
            _ => Err(val),
        }
    }
}

/// Power Manager Wakeup Signals
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PowerManagerWakeUps {
    SysrstCtrlAonWkupReq = 0,
    AdcCtrlAonWkupReq = 1,
    PinmuxAonPinWkupReq = 2,
    PinmuxAonUsbWkupReq = 3,
    AonTimerAonWkupReq = 4,
    SensorCtrlWkupReq = 5,
}

/// Reset Manager Software Controlled Resets
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum ResetManagerSwResets {
    SpiDevice = 0,
    SpiHost0 = 1,
    SpiHost1 = 2,
    Usb = 3,
    UsbAon = 4,
    I2c0 = 5,
    I2c1 = 6,
    I2c2 = 7,
}

/// Power Manager Reset Request Signals
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum PowerManagerResetRequests {
    SysrstCtrlAonRstReq = 0,
    AonTimerAonAonTimerRstReq = 1,
}

/// Clock Manager Software-Controlled ("Gated") Clocks.
///
/// The Software has full control over these clocks.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum GateableClocks {
    /// Clock clk_io_div4_peri in group peri
    IoDiv4Peri = 0,
    /// Clock clk_io_div2_peri in group peri
    IoDiv2Peri = 1,
    /// Clock clk_io_peri in group peri
    IoPeri = 2,
    /// Clock clk_usb_peri in group peri
    UsbPeri = 3,
}

/// Clock Manager Software-Hinted Clocks.
///
/// The Software has partial control over these clocks. It can ask them to stop,
/// but the clock manager is in control of whether the clock actually is stopped.
#[derive(Copy, Clone, PartialEq, Eq)]
#[repr(u32)]
pub enum HintableClocks {
    /// Clock clk_main_aes in group trans
    MainAes = 0,
    /// Clock clk_main_hmac in group trans
    MainHmac = 1,
    /// Clock clk_main_kmac in group trans
    MainKmac = 2,
    /// Clock clk_main_otbn in group trans
    MainOtbn = 3,
}

/// MMIO Region
///
/// MMIO region excludes any memory that is separate from the module
/// configuration space, i.e. ROM, main SRAM, and flash are excluded but
/// retention SRAM, spi_device memory, or usbdev memory are included.
pub const MMIO_BASE_ADDR: usize = 0x40000000;
pub const MMIO_SIZE_BYTES: usize = 0x10000000;