earlgrey/registers/
rstmgr_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for rstmgr.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip/rstmgr/data/autogen/rstmgr.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Read width for crash info
15pub const RSTMGR_PARAM_RD_WIDTH: u32 = 32;
16/// Index width for crash info
17pub const RSTMGR_PARAM_IDX_WIDTH: u32 = 4;
18/// Number of hardware reset requests, inclusive of debug resets and pwrmgr's internal resets
19pub const RSTMGR_PARAM_NUM_HW_RESETS: u32 = 5;
20/// Number of software resets
21pub const RSTMGR_PARAM_NUM_SW_RESETS: u32 = 8;
22/// Number of total reset requests, inclusive of hw/sw, por and low power exit
23pub const RSTMGR_PARAM_NUM_TOTAL_RESETS: u32 = 8;
24/// Number of alerts
25pub const RSTMGR_PARAM_NUM_ALERTS: u32 = 2;
26/// Register width
27pub const RSTMGR_PARAM_REG_WIDTH: u32 = 32;
28
29register_structs! {
30    pub RstmgrRegisters {
31        /// Alert Test Register
32        (0x0000 => pub(crate) alert_test: ReadWrite<u32, ALERT_TEST::Register>),
33        /// Software requested system reset.
34        (0x0004 => pub(crate) reset_req: ReadWrite<u32, RESET_REQ::Register>),
35        /// Device reset reason.
36        (0x0008 => pub(crate) reset_info: ReadWrite<u32, RESET_INFO::Register>),
37        /// Alert write enable
38        (0x000c => pub(crate) alert_regwen: ReadWrite<u32, ALERT_REGWEN::Register>),
39        /// Alert info dump controls.
40        (0x0010 => pub(crate) alert_info_ctrl: ReadWrite<u32, ALERT_INFO_CTRL::Register>),
41        /// Alert info dump attributes.
42        (0x0014 => pub(crate) alert_info_attr: ReadWrite<u32, ALERT_INFO_ATTR::Register>),
43        ///   Alert dump information prior to last reset.
44        (0x0018 => pub(crate) alert_info: ReadWrite<u32, ALERT_INFO::Register>),
45        /// Cpu write enable
46        (0x001c => pub(crate) cpu_regwen: ReadWrite<u32, CPU_REGWEN::Register>),
47        /// Cpu info dump controls.
48        (0x0020 => pub(crate) cpu_info_ctrl: ReadWrite<u32, CPU_INFO_CTRL::Register>),
49        /// Cpu info dump attributes.
50        (0x0024 => pub(crate) cpu_info_attr: ReadWrite<u32, CPU_INFO_ATTR::Register>),
51        ///   Cpu dump information prior to last reset.
52        (0x0028 => pub(crate) cpu_info: ReadWrite<u32, CPU_INFO::Register>),
53        /// Register write enable for software controllable resets.
54        (0x002c => pub(crate) sw_rst_regwen: [ReadWrite<u32, SW_RST_REGWEN::Register>; 8]),
55        /// Software controllable resets.
56        (0x004c => pub(crate) sw_rst_ctrl_n: [ReadWrite<u32, SW_RST_CTRL_N::Register>; 8]),
57        /// A bit vector of all the errors that have occurred in reset manager
58        (0x006c => pub(crate) err_code: ReadWrite<u32, ERR_CODE::Register>),
59        (0x0070 => @END),
60    }
61}
62
63register_bitfields![u32,
64    pub(crate) ALERT_TEST [
65        FATAL_FAULT OFFSET(0) NUMBITS(1) [],
66        FATAL_CNSTY_FAULT OFFSET(1) NUMBITS(1) [],
67    ],
68    pub(crate) RESET_REQ [
69        VAL OFFSET(0) NUMBITS(4) [],
70    ],
71    pub(crate) RESET_INFO [
72        POR OFFSET(0) NUMBITS(1) [],
73        LOW_POWER_EXIT OFFSET(1) NUMBITS(1) [],
74        SW_RESET OFFSET(2) NUMBITS(1) [],
75        HW_REQ OFFSET(3) NUMBITS(5) [],
76    ],
77    pub(crate) ALERT_REGWEN [
78        EN OFFSET(0) NUMBITS(1) [],
79    ],
80    pub(crate) ALERT_INFO_CTRL [
81        EN OFFSET(0) NUMBITS(1) [],
82        INDEX OFFSET(4) NUMBITS(4) [],
83    ],
84    pub(crate) ALERT_INFO_ATTR [
85        CNT_AVAIL OFFSET(0) NUMBITS(4) [],
86    ],
87    pub(crate) ALERT_INFO [
88        VALUE OFFSET(0) NUMBITS(32) [],
89    ],
90    pub(crate) CPU_REGWEN [
91        EN OFFSET(0) NUMBITS(1) [],
92    ],
93    pub(crate) CPU_INFO_CTRL [
94        EN OFFSET(0) NUMBITS(1) [],
95        INDEX OFFSET(4) NUMBITS(4) [],
96    ],
97    pub(crate) CPU_INFO_ATTR [
98        CNT_AVAIL OFFSET(0) NUMBITS(4) [],
99    ],
100    pub(crate) CPU_INFO [
101        VALUE OFFSET(0) NUMBITS(32) [],
102    ],
103    pub(crate) SW_RST_REGWEN [
104        EN_0 OFFSET(0) NUMBITS(1) [],
105    ],
106    pub(crate) SW_RST_CTRL_N [
107        VAL_0 OFFSET(0) NUMBITS(1) [],
108    ],
109    pub(crate) ERR_CODE [
110        REG_INTG_ERR OFFSET(0) NUMBITS(1) [],
111        RESET_CONSISTENCY_ERR OFFSET(1) NUMBITS(1) [],
112        FSM_ERR OFFSET(2) NUMBITS(1) [],
113    ],
114];
115
116// End generated register constants for rstmgr
earlgrey/registers/rstmgr_regs.rs

earlgrey/registers/
rstmgr_regs.rs
