earlgrey/registers/
alert_handler_regs.rs

1// Licensed under the Apache License, Version 2.0 or the MIT License.
2// SPDX-License-Identifier: Apache-2.0 OR MIT
3// Copyright lowRISC contributors 2023.
4
5// Generated register constants for alert_handler.
6// Built for Earlgrey-M2.5.1-RC1-493-gedf5e35f5d
7// https://github.com/lowRISC/opentitan/tree/edf5e35f5d50a5377641c90a315109a351de7635
8// Tree status: clean
9// Build date: 2023-10-18T10:11:37
10
11// Original reference file: hw/top_earlgrey/ip_autogen/alert_handler/data/alert_handler.hjson
12use kernel::utilities::registers::ReadWrite;
13use kernel::utilities::registers::{register_bitfields, register_structs};
14/// Number of alert channels.
15pub const ALERT_HANDLER_PARAM_N_ALERTS: u32 = 65;
16/// Number of LPGs.
17pub const ALERT_HANDLER_PARAM_N_LPG: u32 = 24;
18/// Width of LPG ID.
19pub const ALERT_HANDLER_PARAM_N_LPG_WIDTH: u32 = 5;
20/// Width of the escalation timer.
21pub const ALERT_HANDLER_PARAM_ESC_CNT_DW: u32 = 32;
22/// Width of the accumulation counter.
23pub const ALERT_HANDLER_PARAM_ACCU_CNT_DW: u32 = 16;
24/// Number of classes
25pub const ALERT_HANDLER_PARAM_N_CLASSES: u32 = 4;
26/// Number of escalation severities
27pub const ALERT_HANDLER_PARAM_N_ESC_SEV: u32 = 4;
28/// Number of escalation phases
29pub const ALERT_HANDLER_PARAM_N_PHASES: u32 = 4;
30/// Number of local alerts
31pub const ALERT_HANDLER_PARAM_N_LOC_ALERT: u32 = 7;
32/// Width of ping counter
33pub const ALERT_HANDLER_PARAM_PING_CNT_DW: u32 = 16;
34/// Width of phase ID
35pub const ALERT_HANDLER_PARAM_PHASE_DW: u32 = 2;
36/// Width of class ID
37pub const ALERT_HANDLER_PARAM_CLASS_DW: u32 = 2;
38/// Local alert ID for alert ping failure.
39pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_PINGFAIL: u32 = 0;
40/// Local alert ID for escalation ping failure.
41pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_PINGFAIL: u32 = 1;
42/// Local alert ID for alert integrity failure.
43pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ALERT_INTEGFAIL: u32 = 2;
44/// Local alert ID for escalation integrity failure.
45pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_ESC_INTEGFAIL: u32 = 3;
46/// Local alert ID for bus integrity failure.
47pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_BUS_INTEGFAIL: u32 = 4;
48/// Local alert ID for shadow register update error.
49pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_UPDATE_ERROR: u32 = 5;
50/// Local alert ID for shadow register storage error.
51pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_SHADOW_REG_STORAGE_ERROR: u32 = 6;
52/// Last local alert ID.
53pub const ALERT_HANDLER_PARAM_LOCAL_ALERT_ID_LAST: u32 = 6;
54/// Register width
55pub const ALERT_HANDLER_PARAM_REG_WIDTH: u32 = 32;
56
57register_structs! {
58    pub AlertHandlerRegisters {
59        /// Interrupt State Register
60        (0x0000 => pub(crate) intr_state: ReadWrite<u32, INTR::Register>),
61        /// Interrupt Enable Register
62        (0x0004 => pub(crate) intr_enable: ReadWrite<u32, INTR::Register>),
63        /// Interrupt Test Register
64        (0x0008 => pub(crate) intr_test: ReadWrite<u32, INTR::Register>),
65        /// Register write enable for !!PING_TIMEOUT_CYC_SHADOWED and !!PING_TIMER_EN_SHADOWED.
66        (0x000c => pub(crate) ping_timer_regwen: ReadWrite<u32, PING_TIMER_REGWEN::Register>),
67        /// Ping timeout cycle count.
68        (0x0010 => pub(crate) ping_timeout_cyc_shadowed: ReadWrite<u32, PING_TIMEOUT_CYC_SHADOWED::Register>),
69        /// Ping timer enable.
70        (0x0014 => pub(crate) ping_timer_en_shadowed: ReadWrite<u32, PING_TIMER_EN_SHADOWED::Register>),
71        /// Register write enable for alert enable bits.
72        (0x0018 => pub(crate) alert_regwen: [ReadWrite<u32, ALERT_REGWEN::Register>; 65]),
73        /// Enable register for alerts.
74        (0x011c => pub(crate) alert_en_shadowed: [ReadWrite<u32, ALERT_EN_SHADOWED::Register>; 65]),
75        /// Class assignment of alerts.
76        (0x0220 => pub(crate) alert_class_shadowed: [ReadWrite<u32, ALERT_CLASS_SHADOWED::Register>; 65]),
77        /// Alert Cause Register
78        (0x0324 => pub(crate) alert_cause: [ReadWrite<u32, ALERT_CAUSE::Register>; 65]),
79        /// Register write enable for alert enable bits.
80        (0x0428 => pub(crate) loc_alert_regwen: [ReadWrite<u32, LOC_ALERT_REGWEN::Register>; 7]),
81        /// Enable register for the local alerts
82        (0x0444 => pub(crate) loc_alert_en_shadowed: [ReadWrite<u32, LOC_ALERT_EN_SHADOWED::Register>; 7]),
83        /// Class assignment of the local alerts
84        (0x0460 => pub(crate) loc_alert_class_shadowed: [ReadWrite<u32, LOC_ALERT_CLASS_SHADOWED::Register>; 7]),
85        /// Alert Cause Register for the local alerts
86        (0x047c => pub(crate) loc_alert_cause: [ReadWrite<u32, LOC_ALERT_CAUSE::Register>; 7]),
87        /// Lock bit for Class A configuration.
88        (0x0498 => pub(crate) classa_regwen: ReadWrite<u32, CLASSA_REGWEN::Register>),
89        /// Escalation control register for alert Class A. Can not be modified if !!CLASSA_REGWEN is
90        /// false.
91        (0x049c => pub(crate) classa_ctrl_shadowed: ReadWrite<u32, CLASSA_CTRL_SHADOWED::Register>),
92        /// Clear enable for escalation protocol of Class A alerts.
93        (0x04a0 => pub(crate) classa_clr_regwen: ReadWrite<u32, CLASSA_CLR_REGWEN::Register>),
94        /// Clear for escalation protocol of Class A.
95        (0x04a4 => pub(crate) classa_clr_shadowed: ReadWrite<u32, CLASSA_CLR_SHADOWED::Register>),
96        /// Current accumulation value for alert Class A. Software can clear this register
97        (0x04a8 => pub(crate) classa_accum_cnt: ReadWrite<u32, CLASSA_ACCUM_CNT::Register>),
98        /// Accumulation threshold value for alert Class A.
99        (0x04ac => pub(crate) classa_accum_thresh_shadowed: ReadWrite<u32, CLASSA_ACCUM_THRESH_SHADOWED::Register>),
100        /// Interrupt timeout in cycles.
101        (0x04b0 => pub(crate) classa_timeout_cyc_shadowed: ReadWrite<u32, CLASSA_TIMEOUT_CYC_SHADOWED::Register>),
102        /// Crashdump trigger configuration for Class A.
103        (0x04b4 => pub(crate) classa_crashdump_trigger_shadowed: ReadWrite<u32, CLASSA_CRASHDUMP_TRIGGER_SHADOWED::Register>),
104        /// Duration of escalation phase 0 for Class A.
105        (0x04b8 => pub(crate) classa_phase0_cyc_shadowed: ReadWrite<u32, CLASSA_PHASE0_CYC_SHADOWED::Register>),
106        /// Duration of escalation phase 1 for Class A.
107        (0x04bc => pub(crate) classa_phase1_cyc_shadowed: ReadWrite<u32, CLASSA_PHASE1_CYC_SHADOWED::Register>),
108        /// Duration of escalation phase 2 for Class A.
109        (0x04c0 => pub(crate) classa_phase2_cyc_shadowed: ReadWrite<u32, CLASSA_PHASE2_CYC_SHADOWED::Register>),
110        /// Duration of escalation phase 3 for Class A.
111        (0x04c4 => pub(crate) classa_phase3_cyc_shadowed: ReadWrite<u32, CLASSA_PHASE3_CYC_SHADOWED::Register>),
112        /// Escalation counter in cycles for Class A.
113        (0x04c8 => pub(crate) classa_esc_cnt: ReadWrite<u32, CLASSA_ESC_CNT::Register>),
114        /// Current escalation state of Class A. See also !!CLASSA_ESC_CNT.
115        (0x04cc => pub(crate) classa_state: ReadWrite<u32, CLASSA_STATE::Register>),
116        /// Lock bit for Class B configuration.
117        (0x04d0 => pub(crate) classb_regwen: ReadWrite<u32, CLASSB_REGWEN::Register>),
118        /// Escalation control register for alert Class B. Can not be modified if !!CLASSB_REGWEN is
119        /// false.
120        (0x04d4 => pub(crate) classb_ctrl_shadowed: ReadWrite<u32, CLASSB_CTRL_SHADOWED::Register>),
121        /// Clear enable for escalation protocol of Class B alerts.
122        (0x04d8 => pub(crate) classb_clr_regwen: ReadWrite<u32, CLASSB_CLR_REGWEN::Register>),
123        /// Clear for escalation protocol of Class B.
124        (0x04dc => pub(crate) classb_clr_shadowed: ReadWrite<u32, CLASSB_CLR_SHADOWED::Register>),
125        /// Current accumulation value for alert Class B. Software can clear this register
126        (0x04e0 => pub(crate) classb_accum_cnt: ReadWrite<u32, CLASSB_ACCUM_CNT::Register>),
127        /// Accumulation threshold value for alert Class B.
128        (0x04e4 => pub(crate) classb_accum_thresh_shadowed: ReadWrite<u32, CLASSB_ACCUM_THRESH_SHADOWED::Register>),
129        /// Interrupt timeout in cycles.
130        (0x04e8 => pub(crate) classb_timeout_cyc_shadowed: ReadWrite<u32, CLASSB_TIMEOUT_CYC_SHADOWED::Register>),
131        /// Crashdump trigger configuration for Class B.
132        (0x04ec => pub(crate) classb_crashdump_trigger_shadowed: ReadWrite<u32, CLASSB_CRASHDUMP_TRIGGER_SHADOWED::Register>),
133        /// Duration of escalation phase 0 for Class B.
134        (0x04f0 => pub(crate) classb_phase0_cyc_shadowed: ReadWrite<u32, CLASSB_PHASE0_CYC_SHADOWED::Register>),
135        /// Duration of escalation phase 1 for Class B.
136        (0x04f4 => pub(crate) classb_phase1_cyc_shadowed: ReadWrite<u32, CLASSB_PHASE1_CYC_SHADOWED::Register>),
137        /// Duration of escalation phase 2 for Class B.
138        (0x04f8 => pub(crate) classb_phase2_cyc_shadowed: ReadWrite<u32, CLASSB_PHASE2_CYC_SHADOWED::Register>),
139        /// Duration of escalation phase 3 for Class B.
140        (0x04fc => pub(crate) classb_phase3_cyc_shadowed: ReadWrite<u32, CLASSB_PHASE3_CYC_SHADOWED::Register>),
141        /// Escalation counter in cycles for Class B.
142        (0x0500 => pub(crate) classb_esc_cnt: ReadWrite<u32, CLASSB_ESC_CNT::Register>),
143        /// Current escalation state of Class B. See also !!CLASSB_ESC_CNT.
144        (0x0504 => pub(crate) classb_state: ReadWrite<u32, CLASSB_STATE::Register>),
145        /// Lock bit for Class C configuration.
146        (0x0508 => pub(crate) classc_regwen: ReadWrite<u32, CLASSC_REGWEN::Register>),
147        /// Escalation control register for alert Class C. Can not be modified if !!CLASSC_REGWEN is
148        /// false.
149        (0x050c => pub(crate) classc_ctrl_shadowed: ReadWrite<u32, CLASSC_CTRL_SHADOWED::Register>),
150        /// Clear enable for escalation protocol of Class C alerts.
151        (0x0510 => pub(crate) classc_clr_regwen: ReadWrite<u32, CLASSC_CLR_REGWEN::Register>),
152        /// Clear for escalation protocol of Class C.
153        (0x0514 => pub(crate) classc_clr_shadowed: ReadWrite<u32, CLASSC_CLR_SHADOWED::Register>),
154        /// Current accumulation value for alert Class C. Software can clear this register
155        (0x0518 => pub(crate) classc_accum_cnt: ReadWrite<u32, CLASSC_ACCUM_CNT::Register>),
156        /// Accumulation threshold value for alert Class C.
157        (0x051c => pub(crate) classc_accum_thresh_shadowed: ReadWrite<u32, CLASSC_ACCUM_THRESH_SHADOWED::Register>),
158        /// Interrupt timeout in cycles.
159        (0x0520 => pub(crate) classc_timeout_cyc_shadowed: ReadWrite<u32, CLASSC_TIMEOUT_CYC_SHADOWED::Register>),
160        /// Crashdump trigger configuration for Class C.
161        (0x0524 => pub(crate) classc_crashdump_trigger_shadowed: ReadWrite<u32, CLASSC_CRASHDUMP_TRIGGER_SHADOWED::Register>),
162        /// Duration of escalation phase 0 for Class C.
163        (0x0528 => pub(crate) classc_phase0_cyc_shadowed: ReadWrite<u32, CLASSC_PHASE0_CYC_SHADOWED::Register>),
164        /// Duration of escalation phase 1 for Class C.
165        (0x052c => pub(crate) classc_phase1_cyc_shadowed: ReadWrite<u32, CLASSC_PHASE1_CYC_SHADOWED::Register>),
166        /// Duration of escalation phase 2 for Class C.
167        (0x0530 => pub(crate) classc_phase2_cyc_shadowed: ReadWrite<u32, CLASSC_PHASE2_CYC_SHADOWED::Register>),
168        /// Duration of escalation phase 3 for Class C.
169        (0x0534 => pub(crate) classc_phase3_cyc_shadowed: ReadWrite<u32, CLASSC_PHASE3_CYC_SHADOWED::Register>),
170        /// Escalation counter in cycles for Class C.
171        (0x0538 => pub(crate) classc_esc_cnt: ReadWrite<u32, CLASSC_ESC_CNT::Register>),
172        /// Current escalation state of Class C. See also !!CLASSC_ESC_CNT.
173        (0x053c => pub(crate) classc_state: ReadWrite<u32, CLASSC_STATE::Register>),
174        /// Lock bit for Class D configuration.
175        (0x0540 => pub(crate) classd_regwen: ReadWrite<u32, CLASSD_REGWEN::Register>),
176        /// Escalation control register for alert Class D. Can not be modified if !!CLASSD_REGWEN is
177        /// false.
178        (0x0544 => pub(crate) classd_ctrl_shadowed: ReadWrite<u32, CLASSD_CTRL_SHADOWED::Register>),
179        /// Clear enable for escalation protocol of Class D alerts.
180        (0x0548 => pub(crate) classd_clr_regwen: ReadWrite<u32, CLASSD_CLR_REGWEN::Register>),
181        /// Clear for escalation protocol of Class D.
182        (0x054c => pub(crate) classd_clr_shadowed: ReadWrite<u32, CLASSD_CLR_SHADOWED::Register>),
183        /// Current accumulation value for alert Class D. Software can clear this register
184        (0x0550 => pub(crate) classd_accum_cnt: ReadWrite<u32, CLASSD_ACCUM_CNT::Register>),
185        /// Accumulation threshold value for alert Class D.
186        (0x0554 => pub(crate) classd_accum_thresh_shadowed: ReadWrite<u32, CLASSD_ACCUM_THRESH_SHADOWED::Register>),
187        /// Interrupt timeout in cycles.
188        (0x0558 => pub(crate) classd_timeout_cyc_shadowed: ReadWrite<u32, CLASSD_TIMEOUT_CYC_SHADOWED::Register>),
189        /// Crashdump trigger configuration for Class D.
190        (0x055c => pub(crate) classd_crashdump_trigger_shadowed: ReadWrite<u32, CLASSD_CRASHDUMP_TRIGGER_SHADOWED::Register>),
191        /// Duration of escalation phase 0 for Class D.
192        (0x0560 => pub(crate) classd_phase0_cyc_shadowed: ReadWrite<u32, CLASSD_PHASE0_CYC_SHADOWED::Register>),
193        /// Duration of escalation phase 1 for Class D.
194        (0x0564 => pub(crate) classd_phase1_cyc_shadowed: ReadWrite<u32, CLASSD_PHASE1_CYC_SHADOWED::Register>),
195        /// Duration of escalation phase 2 for Class D.
196        (0x0568 => pub(crate) classd_phase2_cyc_shadowed: ReadWrite<u32, CLASSD_PHASE2_CYC_SHADOWED::Register>),
197        /// Duration of escalation phase 3 for Class D.
198        (0x056c => pub(crate) classd_phase3_cyc_shadowed: ReadWrite<u32, CLASSD_PHASE3_CYC_SHADOWED::Register>),
199        /// Escalation counter in cycles for Class D.
200        (0x0570 => pub(crate) classd_esc_cnt: ReadWrite<u32, CLASSD_ESC_CNT::Register>),
201        /// Current escalation state of Class D. See also !!CLASSD_ESC_CNT.
202        (0x0574 => pub(crate) classd_state: ReadWrite<u32, CLASSD_STATE::Register>),
203        (0x0578 => @END),
204    }
205}
206
207register_bitfields![u32,
208    /// Common Interrupt Offsets
209    pub(crate) INTR [
210        CLASSA OFFSET(0) NUMBITS(1) [],
211        CLASSB OFFSET(1) NUMBITS(1) [],
212        CLASSC OFFSET(2) NUMBITS(1) [],
213        CLASSD OFFSET(3) NUMBITS(1) [],
214    ],
215    pub(crate) PING_TIMER_REGWEN [
216        PING_TIMER_REGWEN OFFSET(0) NUMBITS(1) [],
217    ],
218    pub(crate) PING_TIMEOUT_CYC_SHADOWED [
219        PING_TIMEOUT_CYC_SHADOWED OFFSET(0) NUMBITS(16) [],
220    ],
221    pub(crate) PING_TIMER_EN_SHADOWED [
222        PING_TIMER_EN_SHADOWED OFFSET(0) NUMBITS(1) [],
223    ],
224    pub(crate) ALERT_REGWEN [
225        EN_0 OFFSET(0) NUMBITS(1) [],
226    ],
227    pub(crate) ALERT_EN_SHADOWED [
228        EN_A_0 OFFSET(0) NUMBITS(1) [],
229    ],
230    pub(crate) ALERT_CLASS_SHADOWED [
231        CLASS_A_0 OFFSET(0) NUMBITS(2) [
232            CLASSA = 0,
233            CLASSB = 1,
234            CLASSC = 2,
235            CLASSD = 3,
236        ],
237    ],
238    pub(crate) ALERT_CAUSE [
239        A_0 OFFSET(0) NUMBITS(1) [],
240    ],
241    pub(crate) LOC_ALERT_REGWEN [
242        EN_0 OFFSET(0) NUMBITS(1) [],
243    ],
244    pub(crate) LOC_ALERT_EN_SHADOWED [
245        EN_LA_0 OFFSET(0) NUMBITS(1) [],
246    ],
247    pub(crate) LOC_ALERT_CLASS_SHADOWED [
248        CLASS_LA_0 OFFSET(0) NUMBITS(2) [
249            CLASSA = 0,
250            CLASSB = 1,
251            CLASSC = 2,
252            CLASSD = 3,
253        ],
254    ],
255    pub(crate) LOC_ALERT_CAUSE [
256        LA_0 OFFSET(0) NUMBITS(1) [],
257    ],
258    pub(crate) CLASSA_REGWEN [
259        CLASSA_REGWEN OFFSET(0) NUMBITS(1) [],
260    ],
261    pub(crate) CLASSA_CTRL_SHADOWED [
262        EN OFFSET(0) NUMBITS(1) [],
263        LOCK OFFSET(1) NUMBITS(1) [],
264        EN_E0 OFFSET(2) NUMBITS(1) [],
265        EN_E1 OFFSET(3) NUMBITS(1) [],
266        EN_E2 OFFSET(4) NUMBITS(1) [],
267        EN_E3 OFFSET(5) NUMBITS(1) [],
268        MAP_E0 OFFSET(6) NUMBITS(2) [],
269        MAP_E1 OFFSET(8) NUMBITS(2) [],
270        MAP_E2 OFFSET(10) NUMBITS(2) [],
271        MAP_E3 OFFSET(12) NUMBITS(2) [],
272    ],
273    pub(crate) CLASSA_CLR_REGWEN [
274        CLASSA_CLR_REGWEN OFFSET(0) NUMBITS(1) [],
275    ],
276    pub(crate) CLASSA_CLR_SHADOWED [
277        CLASSA_CLR_SHADOWED OFFSET(0) NUMBITS(1) [],
278    ],
279    pub(crate) CLASSA_ACCUM_CNT [
280        CLASSA_ACCUM_CNT OFFSET(0) NUMBITS(16) [],
281    ],
282    pub(crate) CLASSA_ACCUM_THRESH_SHADOWED [
283        CLASSA_ACCUM_THRESH_SHADOWED OFFSET(0) NUMBITS(16) [],
284    ],
285    pub(crate) CLASSA_TIMEOUT_CYC_SHADOWED [
286        CLASSA_TIMEOUT_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
287    ],
288    pub(crate) CLASSA_CRASHDUMP_TRIGGER_SHADOWED [
289        CLASSA_CRASHDUMP_TRIGGER_SHADOWED OFFSET(0) NUMBITS(2) [],
290    ],
291    pub(crate) CLASSA_PHASE0_CYC_SHADOWED [
292        CLASSA_PHASE0_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
293    ],
294    pub(crate) CLASSA_PHASE1_CYC_SHADOWED [
295        CLASSA_PHASE1_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
296    ],
297    pub(crate) CLASSA_PHASE2_CYC_SHADOWED [
298        CLASSA_PHASE2_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
299    ],
300    pub(crate) CLASSA_PHASE3_CYC_SHADOWED [
301        CLASSA_PHASE3_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
302    ],
303    pub(crate) CLASSA_ESC_CNT [
304        CLASSA_ESC_CNT OFFSET(0) NUMBITS(32) [],
305    ],
306    pub(crate) CLASSA_STATE [
307        CLASSA_STATE OFFSET(0) NUMBITS(3) [
308            IDLE = 0,
309            TIMEOUT = 1,
310            FSMERROR = 2,
311            TERMINAL = 3,
312            PHASE0 = 4,
313            PHASE1 = 5,
314            PHASE2 = 6,
315            PHASE3 = 7,
316        ],
317    ],
318    pub(crate) CLASSB_REGWEN [
319        CLASSB_REGWEN OFFSET(0) NUMBITS(1) [],
320    ],
321    pub(crate) CLASSB_CTRL_SHADOWED [
322        EN OFFSET(0) NUMBITS(1) [],
323        LOCK OFFSET(1) NUMBITS(1) [],
324        EN_E0 OFFSET(2) NUMBITS(1) [],
325        EN_E1 OFFSET(3) NUMBITS(1) [],
326        EN_E2 OFFSET(4) NUMBITS(1) [],
327        EN_E3 OFFSET(5) NUMBITS(1) [],
328        MAP_E0 OFFSET(6) NUMBITS(2) [],
329        MAP_E1 OFFSET(8) NUMBITS(2) [],
330        MAP_E2 OFFSET(10) NUMBITS(2) [],
331        MAP_E3 OFFSET(12) NUMBITS(2) [],
332    ],
333    pub(crate) CLASSB_CLR_REGWEN [
334        CLASSB_CLR_REGWEN OFFSET(0) NUMBITS(1) [],
335    ],
336    pub(crate) CLASSB_CLR_SHADOWED [
337        CLASSB_CLR_SHADOWED OFFSET(0) NUMBITS(1) [],
338    ],
339    pub(crate) CLASSB_ACCUM_CNT [
340        CLASSB_ACCUM_CNT OFFSET(0) NUMBITS(16) [],
341    ],
342    pub(crate) CLASSB_ACCUM_THRESH_SHADOWED [
343        CLASSB_ACCUM_THRESH_SHADOWED OFFSET(0) NUMBITS(16) [],
344    ],
345    pub(crate) CLASSB_TIMEOUT_CYC_SHADOWED [
346        CLASSB_TIMEOUT_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
347    ],
348    pub(crate) CLASSB_CRASHDUMP_TRIGGER_SHADOWED [
349        CLASSB_CRASHDUMP_TRIGGER_SHADOWED OFFSET(0) NUMBITS(2) [],
350    ],
351    pub(crate) CLASSB_PHASE0_CYC_SHADOWED [
352        CLASSB_PHASE0_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
353    ],
354    pub(crate) CLASSB_PHASE1_CYC_SHADOWED [
355        CLASSB_PHASE1_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
356    ],
357    pub(crate) CLASSB_PHASE2_CYC_SHADOWED [
358        CLASSB_PHASE2_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
359    ],
360    pub(crate) CLASSB_PHASE3_CYC_SHADOWED [
361        CLASSB_PHASE3_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
362    ],
363    pub(crate) CLASSB_ESC_CNT [
364        CLASSB_ESC_CNT OFFSET(0) NUMBITS(32) [],
365    ],
366    pub(crate) CLASSB_STATE [
367        CLASSB_STATE OFFSET(0) NUMBITS(3) [
368            IDLE = 0,
369            TIMEOUT = 1,
370            FSMERROR = 2,
371            TERMINAL = 3,
372            PHASE0 = 4,
373            PHASE1 = 5,
374            PHASE2 = 6,
375            PHASE3 = 7,
376        ],
377    ],
378    pub(crate) CLASSC_REGWEN [
379        CLASSC_REGWEN OFFSET(0) NUMBITS(1) [],
380    ],
381    pub(crate) CLASSC_CTRL_SHADOWED [
382        EN OFFSET(0) NUMBITS(1) [],
383        LOCK OFFSET(1) NUMBITS(1) [],
384        EN_E0 OFFSET(2) NUMBITS(1) [],
385        EN_E1 OFFSET(3) NUMBITS(1) [],
386        EN_E2 OFFSET(4) NUMBITS(1) [],
387        EN_E3 OFFSET(5) NUMBITS(1) [],
388        MAP_E0 OFFSET(6) NUMBITS(2) [],
389        MAP_E1 OFFSET(8) NUMBITS(2) [],
390        MAP_E2 OFFSET(10) NUMBITS(2) [],
391        MAP_E3 OFFSET(12) NUMBITS(2) [],
392    ],
393    pub(crate) CLASSC_CLR_REGWEN [
394        CLASSC_CLR_REGWEN OFFSET(0) NUMBITS(1) [],
395    ],
396    pub(crate) CLASSC_CLR_SHADOWED [
397        CLASSC_CLR_SHADOWED OFFSET(0) NUMBITS(1) [],
398    ],
399    pub(crate) CLASSC_ACCUM_CNT [
400        CLASSC_ACCUM_CNT OFFSET(0) NUMBITS(16) [],
401    ],
402    pub(crate) CLASSC_ACCUM_THRESH_SHADOWED [
403        CLASSC_ACCUM_THRESH_SHADOWED OFFSET(0) NUMBITS(16) [],
404    ],
405    pub(crate) CLASSC_TIMEOUT_CYC_SHADOWED [
406        CLASSC_TIMEOUT_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
407    ],
408    pub(crate) CLASSC_CRASHDUMP_TRIGGER_SHADOWED [
409        CLASSC_CRASHDUMP_TRIGGER_SHADOWED OFFSET(0) NUMBITS(2) [],
410    ],
411    pub(crate) CLASSC_PHASE0_CYC_SHADOWED [
412        CLASSC_PHASE0_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
413    ],
414    pub(crate) CLASSC_PHASE1_CYC_SHADOWED [
415        CLASSC_PHASE1_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
416    ],
417    pub(crate) CLASSC_PHASE2_CYC_SHADOWED [
418        CLASSC_PHASE2_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
419    ],
420    pub(crate) CLASSC_PHASE3_CYC_SHADOWED [
421        CLASSC_PHASE3_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
422    ],
423    pub(crate) CLASSC_ESC_CNT [
424        CLASSC_ESC_CNT OFFSET(0) NUMBITS(32) [],
425    ],
426    pub(crate) CLASSC_STATE [
427        CLASSC_STATE OFFSET(0) NUMBITS(3) [
428            IDLE = 0,
429            TIMEOUT = 1,
430            FSMERROR = 2,
431            TERMINAL = 3,
432            PHASE0 = 4,
433            PHASE1 = 5,
434            PHASE2 = 6,
435            PHASE3 = 7,
436        ],
437    ],
438    pub(crate) CLASSD_REGWEN [
439        CLASSD_REGWEN OFFSET(0) NUMBITS(1) [],
440    ],
441    pub(crate) CLASSD_CTRL_SHADOWED [
442        EN OFFSET(0) NUMBITS(1) [],
443        LOCK OFFSET(1) NUMBITS(1) [],
444        EN_E0 OFFSET(2) NUMBITS(1) [],
445        EN_E1 OFFSET(3) NUMBITS(1) [],
446        EN_E2 OFFSET(4) NUMBITS(1) [],
447        EN_E3 OFFSET(5) NUMBITS(1) [],
448        MAP_E0 OFFSET(6) NUMBITS(2) [],
449        MAP_E1 OFFSET(8) NUMBITS(2) [],
450        MAP_E2 OFFSET(10) NUMBITS(2) [],
451        MAP_E3 OFFSET(12) NUMBITS(2) [],
452    ],
453    pub(crate) CLASSD_CLR_REGWEN [
454        CLASSD_CLR_REGWEN OFFSET(0) NUMBITS(1) [],
455    ],
456    pub(crate) CLASSD_CLR_SHADOWED [
457        CLASSD_CLR_SHADOWED OFFSET(0) NUMBITS(1) [],
458    ],
459    pub(crate) CLASSD_ACCUM_CNT [
460        CLASSD_ACCUM_CNT OFFSET(0) NUMBITS(16) [],
461    ],
462    pub(crate) CLASSD_ACCUM_THRESH_SHADOWED [
463        CLASSD_ACCUM_THRESH_SHADOWED OFFSET(0) NUMBITS(16) [],
464    ],
465    pub(crate) CLASSD_TIMEOUT_CYC_SHADOWED [
466        CLASSD_TIMEOUT_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
467    ],
468    pub(crate) CLASSD_CRASHDUMP_TRIGGER_SHADOWED [
469        CLASSD_CRASHDUMP_TRIGGER_SHADOWED OFFSET(0) NUMBITS(2) [],
470    ],
471    pub(crate) CLASSD_PHASE0_CYC_SHADOWED [
472        CLASSD_PHASE0_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
473    ],
474    pub(crate) CLASSD_PHASE1_CYC_SHADOWED [
475        CLASSD_PHASE1_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
476    ],
477    pub(crate) CLASSD_PHASE2_CYC_SHADOWED [
478        CLASSD_PHASE2_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
479    ],
480    pub(crate) CLASSD_PHASE3_CYC_SHADOWED [
481        CLASSD_PHASE3_CYC_SHADOWED OFFSET(0) NUMBITS(32) [],
482    ],
483    pub(crate) CLASSD_ESC_CNT [
484        CLASSD_ESC_CNT OFFSET(0) NUMBITS(32) [],
485    ],
486    pub(crate) CLASSD_STATE [
487        CLASSD_STATE OFFSET(0) NUMBITS(3) [
488            IDLE = 0,
489            TIMEOUT = 1,
490            FSMERROR = 2,
491            TERMINAL = 3,
492            PHASE0 = 4,
493            PHASE1 = 5,
494            PHASE2 = 6,
495            PHASE3 = 7,
496        ],
497    ],
498];
499
500// End generated register constants for alert_handler
earlgrey/registers/alert_handler_regs.rs

earlgrey/registers/
alert_handler_regs.rs
